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參數(shù)資料
| 型號(hào)： | BCM5500 |
| 文件頁(yè)數(shù)： | 1/2頁(yè) |
| 文件大?。?/td> | 43K |
| 代理商： | BCM5500 |
Enhanced IEEE 802.3z Ten Bit Interface (TBI)
allows interfacing to MDC/MDIO enabling
simplification of PCS/MAC ASIC
Speed selectable from 1.0 to 2.5 Gbps per channel
(aggregate user data rate of 3.125 GB) for chassis
backplane systems and front panel transceiver
On-chip “Power On Reset” for initialization.
Additionally, each transceiver can be independently
reset/powered down
Global Configuration Registers to enable/disable
functions such as PLL lock, channel synchronization,
VCO bypass, and DDR
Receiver FIFO is provided for de-skew of the external
and internal clocks. The FIFO also provides the
capability to synchronize the four receiver channels
Internal Pseudo Random Bit Generator (PRBG) is
programmable to facilitate Built In Self Test (BIST)
Built-in data comparator can be enabled to capture
transmitted data and compare that to the receive data
Transmit built-in termination resistor reduces board
design complexity
BCM5500 Applic ations
S U M M A R Y O F B E N E F I T S
MAC
ASIC
MAC
ASIC
MAC
ASIC
MAC
ASIC
Fiber-Optic Receiver
Pre-amplifier
Fiber-Optic Transmitter
Amplifier
Optical
Input
Optical
Output
Fiber-Optic Receiver
Pre-amplifier
Fiber-Optic Transmitter
Amplifier
Optical
Input
Optical
Output
Fiber-Optic Receiver
Pre-amplifier
Fiber-Optic Transmitter
Amplifier
Optical
Input
Optical
Output
Fiber-Optic Receiver
Pre-amplifier
Fiber-Optic Transmitter
Amplifier
Optical
Input
Optical
Output
TX+
TX-
RX+
RX-
1.0-2.5 Gbps
SerDes
CLKRX
CLKTX
Serial
Backplane
ASIC
Driver
1.0-2.5 Gbps
SerDes
1.0-2.5 Gbps
SerDes
1.0-2.5 Gbps
SerDes
BCM5500
1.0-2.5 Gbps
SerDes
1.0-2.5 Gbps
SerDes
1.0-2.5 Gbps
SerDes
1.0-2.5 Gbps
SerDes
BCM5500
Quad Serial Transceiver Supporting 1000B-CX,
1000B-LX, and 1000B-SX Full Duplex Operation
Fully Compliant with the 802.3z Standards
Data Rate Upgradeable to 3.125 GB
0.25 micron Standard CMOS Process Technology,
2.5 V Single Supply
Ultra-Low Jitter (ULJ) Differential LVPECL
Interface
10-Bit Parallel LVTTL Compatible Interface (TBI)
On-Chip Phase-Locked Loop (PLL) Providing Clock
Synthesis from 62.5 or 125 MHz Clock References
Optional Auto Synchronization on all Transceivers
Optional Positive and Negative Comma Character
Detection
Parallel or Serial Loop-Back Mode
BIST Capability
MDC/MDIO Management Interface
Optional 8B/10B Encoder/Decoder (Bypassable)
IEEE 1149.1 (JTAG) Functions
250 mW/Channel Typical Power Dissipation
256-Pin PBGA
B C M 5 5 0 0 F E A T U R E S
10 GBPS S ERIAL HIGH-S PEED T RANS CEIV ER/BACK PLANE S ERDES
PRODUCT
Brief
Brief
B C M5 5 0 0
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