IInput FIFO
Input FIFO
//10B Encoder
8B/10B Encoder
Serializer
Serializer
Clock Recovery
WorClock Recovery
Word Synchronization
TMS
TCK
TDI
TDO
TRSTb
IEEE 1149.1
JTAG
MDIO
MDC
Configuration
Control
R
R
TD0+
TD0-
TXCKO
Clock Multiplier Unit
PLL
RD0+
RD0-
TX[9:0]
TX_CLK
FRST
EWRAP
10B/8B Decoder
De-Serializer
RX[9:0]
COM_DET
RX_CLK0
RX_CLK1
EN_CDET
LCK_REFB
RST
Output FIFO
The Broadcom
BCM5500
is a fully integrated Quad transceiver
housed in a plastic BGA package. Manufactured in a standard
single-poly low-cost CMOS process, the chip provides
aggregate bandwidth for serial transfer of raw data at 10 Gbps.
The chip also provides a physical layer solution of 1.25 to 3.125
Giga Baud (GB) data transfer per channel, and is the world’s
lowest power per channel transceiver (250 mW).
Fully integrated PLL and CDR enables individual channels
to lock to the incoming data. The unique design of the VCO
and CDR blocks have resulted in the world’s lowest jitter
PLL (ULJ).
B C
M 5 5 0 0 O V
E
R
V
I E
W
All receivers can be synchronized using a robust buffer design.
Similarly, the chip offers the option of synchronizing the
transmitters for simultaneous transmission. The transmitter
section accepts 10-bit wide (TBI) parallel LVTTL/SSTL_2
data at 125 MHz byte clock and serializes into LVPECL high
speed serial data for each channel. The receiver section
enables individual channels to lock to the incoming data. The
recovered data is presented at LVTTL/SSTL_2 parallel
outputs. The 8B/10B encoding and 10B/8B decoding of the
PCS layer, speed selection, alignment schemes, VCO and
Synch, and bypass capabilities are addressed through
configuration registers.
For more information please c ontac t us at:
Phone: 949-450-8700, FAX : 949-450-8710
Email: info@broadc om.c om
Visit our web site at: www.broadc om.c om
1999 BROADCOM CORPORATION
BCM5500.0PB8.31.99
Broadcom
and the
Broadcom Logo
are registered trademarks of Broadcom Corporation.
BROADCOM CORPORAT ION
16215 Alton Parkway, P.O. Box 57013
Irvine, California 92619-7013