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參數(shù)資料
| 型號(hào)： | BCM5802 |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | SPECIALTY MICROPROCESSOR CIRCUIT, PQFP144 |
| 封裝： | 28 X 28 MM, QFP-144 |
| 文件頁數(shù)： | 1/41頁 |
| 文件大小： | 571K |
| 代理商： | BCM5802 |
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PRODUCTION SPECIFICATION
■ BCM5802
5802-DS03-R
16215 Alton Parkway P.O. Box 57013 Irvine, California 92619-7013 Phone: 949-450-8700 Fax: 949-450-8710
07/03/02
Single-Chip Security Processor
GENERAL DESCRIP T ION
FE A T U R E S
The BCM5802 Security Processor provides industry-
standard IETF IPsec encryption and authentication
acceler a tion as we ll as I K E / SS L/TLS key setup
acceleration. Engine throughput is over 150 Mbps with
3DES strong encryption and MD5/SHA1 authentication
enabled. Sustained in-system performance with all
features enabled ranges up to 100 Mbps for crypto/
authentication acceleration and 30 1024-bit Diffie-Hellman
(180-bit exponent) key setups per second. The BCM5802
is ideal for cost-sensitive devices, including cable modem
access systems, xDSL access systems, T1/T3 line
security, and 10/100 Mbps ethernet interfaces.
The BCM5802 includes a built-in PCI 2.2 compliant
interface for easy hardware interfacing. It requires zero
external support components, enabling tremendous
system cost savings, and it features a streamlined high-
performance programming model for easy software
integration.
High-performance,
low-cost
security
processor
integrating full IPsec acceleration
Supports DES, 3DES, HMAC-SHA1 and HMAC-MD5
100
Mbps
IPsec
(3DES,
SHA1)
in-system
performance, with new Security Association (SA) per
packet
Unlimited SA support via system memory
Extensive hardware support for IKE/SSL/TLS key
setup acceleration
Public key acceleration unit supports over 30
Diffie-Hellman key exchanges per second
Compatible with SSH IPsec and IKE software
True hardware random number generator
Supports multi-packet processing and pre-fetch of
packet data and context
Aggressive pre-fetch DMA allows multi-packet, multi-
threaded, DMA processing with single PCI writes
Full performance maintained independent of any
reasonable PCI latency
PCI 2.2 interface, 32-bit, 33 MHz
Low-power 3.3V design in 0.35 CMOS technology
144-pin DQFP package
Functional Block Diagram
PCI
Master/Slave
Interface
32-Bit
25-33 MHz
Master Controller
(DMA, Sequencing)
Public Key
Acceleration
3DES/DES
Encryption
SHA-1/MD5
Authentication
True Random
Number Generator
Curr
ent
Cont
ex
t
Pr
ef
e
tch
Co
nt
ext
Buf
fe
r
PCI
Bus
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