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2010.10 - Rev.A
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Technical Note
6/11
BD00IA5WEFJ
Stable area characteristics
(Characteristics example)
●
Heat Loss
Thermal design should allow operation within the following conditions. Note that the temperatures listed are the allowed
temperature limits, and thermal design should allow sufficient margin from the limits.
1. Ambient temperature Ta can be no higher than 85℃.
2. Chip junction temperature (Tj) can be no higher than 150℃.
Chip junction temperature can be determined as follows:
①
Calculation based on ambient temperature (Ta)
Tj=Ta+θj-a×W
<
Reference values>
θ
j-a:HTSOP-J8 153.2℃/W
113.6℃/W
59.2℃/W
33.3℃/W
1-layer substrate (copper foil density 0mm×0mm)
2-layer substrate (copper foil density 15mm×15mm)
2-layer substrate (copper foil density 70mm×70mm)
4-layer substrate (copper foil density 70mm×70mm)
Substrate size: 70×70×1.6mm
3 (substrate with thermal via)
Most of the heat loss that occurs in the BD00IA5WEFJ is generated from the output Pch FET. Power loss is determined by
the total Vcc-Vo voltage and output current. Be sure to confirm the system input and output voltage and the output current
conditions in relation to the heat dissipation characteristics of the VIN and Vo in the design. Bearing in mind that heat
dissipation may vary substantially depending on the substrate employed (due to the power package incorporated in the
BD00IA5WEFJ make certain to factor conditions such as substrate size into the thermal design.
Power consumption (W) = Input voltage (VCC)- Output voltage (Vo)
×
Io(Ave)
Example) Where VCC=3.3V, VO=2.5V, Io(Ave) = 0.1A,
Power consumption (W) = 3.3(V)-2.5(V) ×0.1(A)
=0.08(W)
●
About equivalent series resistance ESR (ceramic capacitor etc.)
Capacitor usually has ESR(Equivalent Series Resistance), and
operates stable in ESR-OUT range, showed right. Generally, ESR of
ceramic, tantalum and electronic capacitor etc. is different for each,
so please be sure to check a capacitor which is going to use, and
use it inside the stable range, showed right. Then, please evaluate
for the actual application
0.01
0.1
1
10
100
0
50
100
150
200
IOUT [mA]
ESR
[
]
Capacity-Bias characteristics