參數(shù)資料
型號(hào): BT849A
英文描述: Single-Chip Video Capture for PCI
中文描述: 單芯片的PCI視頻捕捉
文件頁(yè)數(shù): 97/141頁(yè)
文件大?。?/td> 1149K
代理商: BT849A
第1頁(yè)第2頁(yè)第3頁(yè)第4頁(yè)第5頁(yè)第6頁(yè)第7頁(yè)第8頁(yè)第9頁(yè)第10頁(yè)第11頁(yè)第12頁(yè)第13頁(yè)第14頁(yè)第15頁(yè)第16頁(yè)第17頁(yè)第18頁(yè)第19頁(yè)第20頁(yè)第21頁(yè)第22頁(yè)第23頁(yè)第24頁(yè)第25頁(yè)第26頁(yè)第27頁(yè)第28頁(yè)第29頁(yè)第30頁(yè)第31頁(yè)第32頁(yè)第33頁(yè)第34頁(yè)第35頁(yè)第36頁(yè)第37頁(yè)第38頁(yè)第39頁(yè)第40頁(yè)第41頁(yè)第42頁(yè)第43頁(yè)第44頁(yè)第45頁(yè)第46頁(yè)第47頁(yè)第48頁(yè)第49頁(yè)第50頁(yè)第51頁(yè)第52頁(yè)第53頁(yè)第54頁(yè)第55頁(yè)第56頁(yè)第57頁(yè)第58頁(yè)第59頁(yè)第60頁(yè)第61頁(yè)第62頁(yè)第63頁(yè)第64頁(yè)第65頁(yè)第66頁(yè)第67頁(yè)第68頁(yè)第69頁(yè)第70頁(yè)第71頁(yè)第72頁(yè)第73頁(yè)第74頁(yè)第75頁(yè)第76頁(yè)第77頁(yè)第78頁(yè)第79頁(yè)第80頁(yè)第81頁(yè)第82頁(yè)第83頁(yè)第84頁(yè)第85頁(yè)第86頁(yè)第87頁(yè)第88頁(yè)第89頁(yè)第90頁(yè)第91頁(yè)第92頁(yè)第93頁(yè)第94頁(yè)第95頁(yè)第96頁(yè)當(dāng)前第97頁(yè)第98頁(yè)第99頁(yè)第100頁(yè)第101頁(yè)第102頁(yè)第103頁(yè)第104頁(yè)第105頁(yè)第106頁(yè)第107頁(yè)第108頁(yè)第109頁(yè)第110頁(yè)第111頁(yè)第112頁(yè)第113頁(yè)第114頁(yè)第115頁(yè)第116頁(yè)第117頁(yè)第118頁(yè)第119頁(yè)第120頁(yè)第121頁(yè)第122頁(yè)第123頁(yè)第124頁(yè)第125頁(yè)第126頁(yè)第127頁(yè)第128頁(yè)第129頁(yè)第130頁(yè)第131頁(yè)第132頁(yè)第133頁(yè)第134頁(yè)第135頁(yè)第136頁(yè)第137頁(yè)第138頁(yè)第139頁(yè)第140頁(yè)第141頁(yè)
87
C
ONTROL
R
EGISTER
D
EFINITIONS
Command and Status Register
L848A_A
Bt848/848A/849A
Single-Chip Video Capture for PCI
Command and Status Register
PCI Configuration Header Location 0x04
The Command[15:0] register provides control over ability to generate and respond to PCI cycles. When a zero is writ-
ten to this register, Bt848 is logically disconnected from the PCI bus except for configuration cycles. The unused bits
in this register are set to a logical zero. The Status[31:16] register is used to record status information regarding PCI
bus related events.
Bits
Type
Default
Name
Description
[31]
RR
0
Detected Parity
Error
Set when a parity error is detected, in the address or data, regard-
less of the Parity Error Response control bit.
[30]
RR
0
Signaled
System Error
Set when SERR is asserted.
[29]
RR
0
Received
Master Abort
Set when master transaction is terminated with Master Abort.
[28]
RR
0
Received
Target Abort
Set when master transaction is terminated with Target Abort.
[27]
RR
0
Signaled Target
Abort
Set when target terminates transaction with Target Abort. This
occurs when detecting an address parity error.
[26:25]
RO
01
Address Decode
Time
Responds with medium DEVSEL timing.
[24]
RR
0
Data Parity
Reported
A value of 1 indicates that the bus master asserted PERR during
a read transaction or observed PERR asserted by target when
writing data to target. The Parity Error Response bit in the com-
mand register must have been enabled.
[23]
RO
1
FB2B Capable
Target capable of fast back-to-back transactions.
[8]
RW
0
SERR enable
A value of 1 enables the SERR driver.
[6]
RW
0
Parity Error
Response
A value of 1 enables parity error reporting.
[2]
RW
0
Bus Master
A value of 1 enables Bt848 to act as a bus initiator.
[1]
RW
0
Memory Space
A value of 1 enables response to Memory space accesses (target
decode to memory mapped registers).
相關(guān)PDF資料
PDF描述
BT8510EPJC PCM Transceiver
BT857KPJ Color Encoder Circuit
BT8958EHJ50 xDSL Interface
BT8953AEPFC xDSL Interface
BT8953AEPJ xDSL Interface
相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
BT849AKPF 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Single-Chip Video Capture for PCI
BT850-SA 功能描述:BTV4.2 DUAL MODE USB HCI MODULE 制造商:laird - wireless & thermal systems 系列:* 零件狀態(tài):在售 標(biāo)準(zhǔn)包裝:1
BT850-SA-T/R 功能描述:BTV4.2 DUAL MODE USB HCI MODULE 制造商:laird - wireless & thermal systems 系列:* 零件狀態(tài):在售 標(biāo)準(zhǔn)包裝:2,500
BT850-ST 功能描述:BTV4.2 DUAL MODE USB HCI MODULE 制造商:laird - wireless & thermal systems 系列:* 零件狀態(tài):在售 標(biāo)準(zhǔn)包裝:1
BT850-ST-T/R 功能描述:BTV4.2 DUAL MODE USB HCI MODULEE 制造商:laird - wireless & thermal systems 系列:* 零件狀態(tài):在售 標(biāo)準(zhǔn)包裝:2,500