- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄166576 > BU-61703F3-490Z (DATA DEVICE CORP) 2 CHANNEL(S), 1M bps, MIL-STD-1553 CONTROLLER, CQFP72 PDF資料下載
參數(shù)資料
| 型號(hào)： | BU-61703F3-490Z |
| 廠商： | DATA DEVICE CORP |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 2 CHANNEL(S), 1M bps, MIL-STD-1553 CONTROLLER, CQFP72 |
| 封裝： | CERAMIC, QFP-72 |
| 文件頁數(shù)： | 42/54頁 |
| 文件大?。?/td> | 576K |
| 代理商： | BU-61703F3-490Z |
第1頁第2頁第3頁第4頁第5頁第6頁第7頁第8頁第9頁第10頁第11頁第12頁第13頁第14頁第15頁第16頁第17頁第18頁第19頁第20頁第21頁第22頁第23頁第24頁第25頁第26頁第27頁第28頁第29頁第30頁第31頁第32頁第33頁第34頁第35頁第36頁第37頁第38頁第39頁第40頁第41頁當(dāng)前第42頁第43頁第44頁第45頁第46頁第47頁第48頁第49頁第50頁第51頁第52頁第53頁第54頁
47
Data Device Corporation
www.ddc-web.com
BU-61703/61705
D1 web-09/02-0
DESCRIPTION
SIGNAL
TABLE 16. CLOCK INPUT
Clock Input. The clock frequency must be designated by means of the CLK_SEL_1 and CLK_SEL_0 inputs.
CLK_IN (I)
30
PIN
These two inputs are used to designate the SSRT's clock frequency, as follows:
CLK_SEL_1
CLK_SEL_0
Clock Frequency
0
10 MHz
0
1
20 MHz
1
0
12 MHz
1
16 MHz
CLK_SEL_1 (I)
CLK_SEL_0 (I)
66
8
DESCRIPTION
XCVR_TP
(RESET*)
XCVR_TP
(READOUTA)
P5(*)
P3(*)
SIGNAL
TABLE 17. FACTORY TEST
XCVR_TP
(ZAP VOLTA)
P1(*)
PIN
XCVR_TP
(READOUTB)
P2(*)
For factory test only. Do not connect for normal operation.
XCVR_TP
(ZAP VOLTB)
XCVR_TP
(CLOCK)
P6(*)
P4(*)
(*) Note that the Test Output pins are pads located on the bottom of the package.
DESCRIPTION
Transmitter inhibit input for the MIL-STD-1553 transmitters. For normal operation, this input should be connected to logic
"0". To force a shutdown of the Channel A and Channel B transmitters, a value of logic "1" should be applied to this input.
TX_INH (I)
59
Broadcast Enable. If this input is logic "1", the SSRT will recognize RT address 31 as the broadcast address. If this input
is logic "0", the SSRT will not recognize RT address 31 as the broadcast address; however, in this configuration, RT
address 31 may be used as a standard RT address.
BRO_ENA (I)
63
Auto-configure input. If connected to logic "1", then the auto-configure option is disabled, and the six configuration para-
meters revert to their default values as listed in TABLE 2. Note that the default condition for each configuration parameter
is enabled (for the MIL-STD-1553A/B protocol selection, -1553B is the default).
If AUTO_CFG is connected to logic "0", then the configuration parameters are transferred over D5-D0 during a DMA read
data transfer, when RTACTIVE and DTACK are logic "0", following MSTCLR transitioning from logic "0" to logic "1". Each
of the configuration parameters is enabled if the SSRT reads a value of logic "1" for the respective data bit.
AUTO_CFG (I)
70
Master Clear. Negative true Reset input, asserted low following power turn-on. When coming out of a “reset” condition,
note that the risetime of MSTCLR must be less than 10 s.
MSTCLR (I)
2
SIGNAL
TABLE 15. CONTROL INPUTS
PIN
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| BU-61703F3-890Y | 2 CHANNEL(S), 1M bps, MIL-STD-1553 CONTROLLER, CQFP72 |
| BU-61703F4-400W | 2 CHANNEL(S), 1M bps, MIL-STD-1553 CONTROLLER, CQFP72 |
| BU-61703G3-400Q | 2 CHANNEL(S), 1M bps, MIL-STD-1553 CONTROLLER, CQFP72 |
| BU-61703G3-590K | 2 CHANNEL(S), 1M bps, MIL-STD-1553 CONTROLLER, CQFP72 |
| BU-61703G4-200K | 2 CHANNEL(S), 1M bps, MIL-STD-1553 CONTROLLER, CQFP72 |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| BU-61705 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:MIL-STD-1553 Components |Simple System RT |
| BU-61740B3NEW | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:MIL-STD-1553 Components |μ-ACE (Micro-ACE?) |
| BU-61743 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:MIL-STD-1553 Components |Enhanced Mini-ACE? |
| BU-61743F3-100 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Telecommunication IC |
| BU-61743F3-110 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Telecommunication IC |
發(fā)布緊急采購，3分鐘左右您將得到回復(fù)。