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參數(shù)資料
| 型號(hào)： | BU-61703G4-162Q |
| 廠商： | DATA DEVICE CORP |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 2 CHANNEL(S), 1M bps, MIL-STD-1553 CONTROLLER, MQFP72 |
| 封裝： | 1 X 1 INCH, GULL WING, PACKAGE-72 |
| 文件頁數(shù)： | 50/52頁 |
| 文件大?。?/td> | 367K |
| 代理商： | BU-61703G4-162Q |
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7
In burst mode, a DMA handshake will not be initiated until after all
data words have been received over the 1553 data bus and stored
into the SSRT's internal FIFO. After the handshake has been
negotiated, the SSRT will burst the contents of the FIFO to the
local bus (D0-D15). After the reception of a valid non-mode code
receive command word followed by the correct number of valid
data words and assuming that all words are successfully trans-
ferred to the subsystem, a negative pulse will be asserted on the
output Good Block Received (
). The width of this pulse is two
clock cycles.
RT-TO-RT TRANSFER ERRORS
For the case where the SSRT is the receiving RT of an RT-to-RT
transfer, if the transmitting RT does not respond within the speci-
fied time period, the SSRT will determine that a timeout condition
has occurred. The value of the SSRT's RT-to-RT timeout timer is in
the range from 17.5 to 18.5 s, and is specified from the mid-par-
ity bit crossing of the transmit command word to the mid-sync
crossing of the transmitting RT's status word. In the case of an RT-
to-RT timeout, the SSRT will not respond and the RT-TO-RT NO
TRANSFER TIMEOUT bit (bit 2) of the SSRT's BIT Word will be
set to logic "1".
Also, if the SSRT is the receiving RT for an RT-to-RT transfer, and
the
bit of the second command word is logic "0", or the RT
address field for the transmit command is the same as for the
receive command, or the subaddress for the transmit command is
00000 or 11111, the BU-61703/5 will not respond, and will set the
RT-to-RT SECOND COMMAND ERROR bit (bit 1) of the RT BIT
word to logic "1".
RT STATUS, ERROR HANDLING, AND MESSAGE
TIMING SIGNALS
Message transfers and transfer errors are indicated by means of
the
,
, and
error indication
outputs. Additional error detection and indication mechanisms
include updating of the internal command, RT status and BIT word
registers.
The BU-61703/5 provides a number of timing signals during the
processing of 1553 messages.
is asserted low when a
new command is received. At the end of a message (either valid
or invalid),
transitions from low to high.
As discussed above,
will be asserted low if the subsys-
tem fails to respond to
within the maximum amount of
time (10 s).
Following the last data word transfer for a valid non-mode code
receive message (for either non-burst mode or burst mode),
will be asserted low for two clock cycles.
GBR
DTREQ
FAIL
_
HS
INCMD
RTFAIL
ERR
_
MSG
FAIL
_
HS
INCMD
R
/
T
GBR
BUSY
The external subsystem may control the SSRT's Busy RT status
word bit by means of the
input signal. The SSRT samples
approximately 2 s following the mid-parity bit zero cross-
ing of the received Command Word. If
is sampled low for a
particular message, the value of the busy bit transmitted in the
SSRT's status word will be logic "1". If
is sampled high for
a particular message, the value of the busy bit transmitted in the
SSRT's status word will be logic "0".
If the RT responds to a transmit command with a busy bit of logic
"1", the status word will be transmitted, but no data words will be
transmitted by the SSRT. If the SSRT responds to a receive com-
mand with a busy bit of logic "1", data words will be transferred to
the external subsystem (although these may be blocked by means
of external logic).
Similar to
, it is possible to cause the SSRT to respond
with Busy for specific command words (only), by means of an
external PROM, RAM, or PLD device.
TRANSMIT COMMAND (RT-TO-BC TRANSFER)
If the BU-61703/5 receives a valid Transmit command word that
the subsystem determines is legal (input signal
is high)
and the subsystem is not BUSY (input signal
is high), the
BU-61703/5 will initiate a transmit data response following trans-
mission of its status word. This entails a handshake/read cycle for
each data word transmitted, with the number of data words to be
transmitted specified by the word count field of the transmit com-
mand word.
If
is sampled low, the Message Error bit will be set in the
SSRT's status word. No data words will be transmitted following
transmission of the status word to an illegalized transmit com-
mand. A low on the
input will set the busy bit in the Status
Word; in this instance, only the status word will be transmitted, with
no data words.
RECEIVE COMMAND (BC-TO-RT TRANSFER)
In non-burst mode, a DMA handshake will be initiated for each
data word received from the 1553 data bus. If successful, the
respective handshake will be followed by a corresponding write
cycle. A handshake timeout will not terminate transfer attempts for
the remaining data words, error flagging or Status Word transmis-
sion. After the reception of a valid non-mode code receive
Command Word followed by the correct number of valid Data
Words and assuming that all words are successfully transferred to
the subsystem, a negative pulse will be asserted on the Good
Block Received (
) output. The width of this pulse is two clock
cycles.
GBR
BUSY
ILLEGAL
BUSY
ILLEGAL
BUSY
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| BU-61703G4-162S | 2 CHANNEL(S), 1M bps, MIL-STD-1553 CONTROLLER, MQFP72 |
| BU-61703G4-172K | 2 CHANNEL(S), 1M bps, MIL-STD-1553 CONTROLLER, MQFP72 |
| BU-61703G4-172Q | 2 CHANNEL(S), 1M bps, MIL-STD-1553 CONTROLLER, MQFP72 |
| BU-61703G4-172S | 2 CHANNEL(S), 1M bps, MIL-STD-1553 CONTROLLER, MQFP72 |
| BU-61703G4-172W | 2 CHANNEL(S), 1M bps, MIL-STD-1553 CONTROLLER, MQFP72 |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
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| BU-61705 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:MIL-STD-1553 Components |Simple System RT |
| BU-61740B3NEW | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:MIL-STD-1553 Components |μ-ACE (Micro-ACE?) |
| BU-61743 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:MIL-STD-1553 Components |Enhanced Mini-ACE? |
| BU-61743F3-100 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Telecommunication IC |
| BU-61743F3-110 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Telecommunication IC |
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