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| 型號(hào)： | BU-61703G4-172K |
| 廠商： | DATA DEVICE CORP |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 2 CHANNEL(S), 1M bps, MIL-STD-1553 CONTROLLER, MQFP72 |
| 封裝： | 1 X 1 INCH, GULL WING, PACKAGE-72 |
| 文件頁數(shù)： | 16/52頁 |
| 文件大?。?/td> | 367K |
| 代理商： | BU-61703G4-172K |
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23
TABLE FOR FIGURE 9. SSRT DMA WRITE (BURST MODE) TIMING
VALUE @ 5 Volts
VALUE @ 3.3 Volts
UNITS
REF
DESCRIPTION
CLOCK
FREQUENCY
MIN
TYP
MAX
MIN
TYP
MAX
t1
CLOCK IN rising to DTREQ low
ALL
40
ns
t2
DTREQ falling to DTGRT low
ALL
10
s
20 MHz
60
ns
16 MHz
85
ns
12 MHz
127
ns
t3
CWC setup time prior to MEMWR falling for first
word of burst transfer (see Note 1)
10 MHz
160
ns
t4
DTGRT low setup prior to CLOCK IN rising edge
ALL
10
15
ns
20 MHz
100
105
ns
16 MHz
113
118
ns
12 MHz
133
138
ns
t5
DTGRT falling to DTACK low
10 MHz
150
155
ns
t6
CLOCK IN rising to DTACK low
ALL
40
ns
t7
Data output valid following CLOCK IN
ALL
40
ns
t8
DTGRT hold time following DTACK falling
ALL
30
ns
20 MHz
290
300
290
300
ns
16 MHz
365
375
365
375
ns
12 MHz
490
500
490
500
ns
t9
DTACK low pulse width (based on a two data
word transfer)
(see Note 2)
10 MHz
590
600
590
600
ns
20 MHz
10
ns
16 MHz
22
ns
12 MHz
43
ns
t10
Data output setup time prior to MEMWR low
10 MHz
60
ns
t11
CLOCK IN rising to MEMWR low
ALL
40
ns
20 MHz
40
50
40
50
ns
16 MHz
52.5
62.5
52.5
62.5
ns
12 MHz
73.3
83.3
73.3
83.3
ns
t12
MEMWR low pulse width
10 MHz
90
100
90
100
ns
t13
CLOCK IN rising to MEMWR high
ALL
30
40
ns
20 MHz
20
10
ns
16 MHz
33
23
ns
12 MHz
53
43
ns
t14
Data output and CWC hold time following
MEMWR high
10 MHz
70
60
ns
t15
Data output hold time following CLOCK IN rising
ALL
10
15
ns
20 MHz
10
ns
16 MHz
23
ns
12 MHz
43
ns
t16
CWC (all but first data word) setup time prior to
MEMWR low
10 MHz
60
ns
t17
CLOCK IN rising to DTREQ and DTACK high
ALL
30
40
ns
t18
Data output signal Tri-State following CLOCK IN
rising
ALL
40
ns
t19
CLOCK IN rising to GBR falling edge
ALL
40
ns
20 MHz
90
100
90
100
ns
16 MHz
115
125
115
125
ns
12 MHz
157
167
157
167
ns
t20
GBR low pulse width
10 MHz
190
200
190
200
ns
t21
INCMD rising following CLOCK IN rising
(see Note 3)
ALL
30
40
ns
Notes:
1. Assume DTGRT is low at the time that DTREQ is asserted low. If not, then this time will increase by the amount of
the DTREQ(low)-to-DTGRT(low) delay.
2. DTACK pulse width is 3 clock cycles per data word transfer
3. Rising edge of INCMD will immediately follow the rising edge of GBR only for a broadcast message. For a non-broadcast message, the rising
edge of INCMD will occur after the mid-parity crossing of the RT status response. This additional delay time is approximately 96 clock
cycles: 9.6 s at 10 MHz, 8 s at 12 MHz, 6.0 s at 16 MHz, or 4.8 s at 20 MHz.
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