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參數(shù)資料
| 型號： | BU-62743G3-460Q |
| 廠商： | DATA DEVICE CORP |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 2 CHANNEL(S), 1M bps, MIL-STD-1553 CONTROLLER, CQFP72 |
| 封裝： | 1 INCH, CERAMIC, QFP-72 |
| 文件頁數(shù)： | 11/99頁 |
| 文件大小： | 578K |
| 代理商： | BU-62743G3-460Q |
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Data Device Corporation
62743_pre7_noSA-DB.DOC
www.ddc-web.com
8-07-02
19
Strobe or Request signal is asserted. Four possible FAILSAFE Modes
determine how this situation is handled:
Table 11. FAILSAFE MODE
BIT 17
BIT 16
FAILSAFE MODE
0
FailSafe Off
0
1
FailSafe Retry
1
0
FailSafe Halt
1
FailSafe Skip
NOTE: Failsafe errors are extremely unlikely.
MODE 1 - FAILSAFE OFF. PCI Enhanced Mini-ACE will wait indefinitely for the
transaction to complete. The local bus could hang as a result. The FAILSAFE
ERROR bit and interrupt will not be generated even if the enable bit is set.
MODE 2 - FAILSAFE RETRY. PCI Enhanced Mini-ACE will retry the transfer on
the local bus when the FAILSAFE timer times out.
MODE 3 - FAILSAFE HALT. Once the FAILSAFE timer times out, all future
transfers will be terminated with a target abort until the PCI master clears the
interrupt.
MODE 4 - FAILSAFE SKIP. Once the FAILSAFE timer times out, the current
transaction is discarded or skipped and the next transaction, whether a stored
write in the FIFO or a new transaction, will be attempted.
BITS 15-0 ARE RESERVED: Write these bits as 0s.
Table 12. REG2 Fail-Safe Timer Register
(Read 808h)
BIT
DESCRIPTION
31 (MSB)
0
16
0
15
FAIL-SAFE TIMER COUNT - BIT 15 (MSB)
0 (LSB)
FAIL-SAFE TIMER COUNT - BIT 0 (LSB)
FAIL-SAFE TIMER COUNT: Read this register to obtain the current value of the
fail-safe timer. Default is 8400h.
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