參數(shù)資料
型號(hào)： BU-62743G3-460Q
廠商： DATA DEVICE CORP
元件分類： 微控制器/微處理器
英文描述： 2 CHANNEL(S), 1M bps, MIL-STD-1553 CONTROLLER, CQFP72
封裝： 1 INCH, CERAMIC, QFP-72
文件頁(yè)數(shù)： 35/99頁(yè)
文件大小： 578K
代理商： BU-62743G3-460Q
Data Device Corporation
62743_pre7_noSA-DB.DOC
www.ddc-web.com
8-07-02
40
Note that the pointer parameter referencing the first word of a message’s
control/status block (the BC Control Word) must contain an address value that is
modulo 8. Also, note that if the message is an RT-to-RT transfer, the pointer
parameter ) must contain an address value that is modulo 16.
Op Codes. The instruction list pointer register references a pair of words in the
BC instruction list: an op code word, followed by a parameter word. The format of
the op code word, which is illustrated in Figure 3, includes a 5-bit op code field and
a 5-bit condition code field. The op code identifies the instruction to be executed by
the BC message sequence controller.
Most of the operations are conditional, with execution dependent on the contents
of the condition code field. Bits 3-0 of the condition code field identifies the
particular condition. Bit 4 of the condition code field identifies the logic sense (“1”
or “0”) of the selected condition code on which the conditional execution is
dependent. Table 52 lists all the op codes, along with their respective mnemonic,
code value, parameter, and description. Table 53 defines all the condition codes.
Eight of the condition codes (8 through F) are set or cleared as the result of the
most recent message. The other eight are defined as “General Purpose” condition
codes GP0 through GP7. There are three mechanisms for programming the
values of the General Purpose Condition Code bits: (1) They may be set, cleared,
or toggled by the host processor, by means of the BC GENERAL PURPOSE
FLAG REGISTER; (2) they may be set, cleared, or toggled by the BC message
sequence control processor, by means of the GP Flag Bits (FLG) instruction; and
(3) GP0 and GP1 only (but none of the others) may be set or cleared by means of
the BC message sequence control processor’s Compare Frame Timer (CFT) or
Compare Message Timer (CMT) instructions.
The host processor also has read-only access to the BC condition codes by
means of the BC CONDITION CODE REGISTER.
Note that four (4) instructions are unconditional. These are Compare to Frame
Timer (CFT), Compare to Message Timer (CMT), GP Flag Bits (FLG), and
Execute and Flip (XQF). For these instructions, the Condition Code Field is “don’t
care”. That is, these instructions are always executed, regardless of the result of
the condition code test.
All other instructions are conditional. That is, they will only be executed if the
condition code specified by the condition code field in the op code word tests true.
If the condition code field tests false, the instruction list pointer will skip down to the
next instruction.
As shown in
Table 52, many of the operations include a single-word parameter. For
an XEQ (execute message) operation, the parameter is a pointer to the start of the
message’s control/status block. For other operations, the parameter may be an
address, a time value, an interrupt pattern, a mechanism to set or clear general
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