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參數(shù)資料
| 型號： | BU-62843F4-140Z |
| 廠商： | DATA DEVICE CORP |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 2 CHANNEL(S), 1M bps, MIL-STD-1553 CONTROLLER, CQFP72 |
| 封裝： | 1 INCH, CERAMIC, QFP-72 |
| 文件頁數(shù)： | 55/99頁 |
| 文件大?。?/td> | 578K |
| 代理商： | BU-62843F4-140Z |
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Data Device Corporation
62743_pre7_noSA-DB.DOC
www.ddc-web.com
8-07-02
59
over from FFFF(hex) to 0. Other time tag options include the capabilities to clear
the time tag register following receipt of a Synchronize (without data) mode
command and/or to set the time tag following receipt of a Synchronize (with data)
mode command. For that latter, there is an added option to filter the “set” capability
based on the LSB of the received data word being equal to logic “0”.
RT INTERRUPTS
The PCI Enhanced Mini-ACE offers a great deal of flexibility in terms of RT
interrupt processing. By means of the PCI Enhanced Mini-ACE’s two Interrupt
Mask Registers, the RT may be programmed to issue interrupt requests for the
following events/conditions: End-of-(every)Message, Message Error, Selected
(transmit or receive) Subaddress, 100% Circular Buffer Rollover, 50% Circular
Buffer Rollover, 100% Descriptor Stack Rollover, 50% Descriptor Stack Rollover,
Selected Mode Code, Transmitter Timeout, Illegal Command, and Interrupt
Status Queue Rollover.
Interrupts for 50% Rollovers of Stacks, Circular Buffers. The PCI Enhanced
Mini-ACE RT and Monitor are capable of issuing host interrupts when a
subaddress circular buffer pointer or stack pointer crosses its mid-point boundary.
For RT circular buffers, this is applicable for both transmit and receive
subaddresses. Reference Figure 8. There are four interrupt mask and interrupt
status register bits associated with the 50% rollover function:
(1) RT circular buffer;
(2) RT command (descriptor) stack;
(3) Monitor command (descriptor) stack; and
(4) Monitor data stack.
The 50% rollover interrupt is beneficial for performing bulk data transfers. For
example, when using circular buffering for a particular receive subaddress, the
50% rollover interrupt will inform the host processor when the circular buffer is half
full. At that time, the host may proceed to read the received data words in the
upper half of the buffer, while the PCI Enhanced Mini-ACE RT writes received data
words to the lower half of the circular buffer. Later, when the RT issues a 100%
circular buffer rollover interrupt, the host can proceed to read the received data
from the lower half of the buffer, while the PCI Enhanced Mini-ACE RT continues
to write received data words to the upper half of the buffer.
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| BU-62843F4-300S | 2 CHANNEL(S), 1M bps, MIL-STD-1553 CONTROLLER, CQFP72 |
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