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參數(shù)資料
| 型號(hào)： | BU-65566M19N |
| 廠商： | DATA DEVICE CORP |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 4 CHANNEL(S), MIL-STD-1553 CONTROLLER, XMA64 |
| 文件頁(yè)數(shù)： | 10/15頁(yè) |
| 文件大?。?/td> | 502K |
| 代理商： | BU-65566M19N |
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Data Device Corporation
www.ddc-web.com
BU-65566
F-04/06-0
INTRODUCTION
The BU-65566 is a single- or multi-channel MIL-STD-1553
66MHz PMC card built in accordance with IEEE PMC Physical
and Environmental Layers Standard. The BU-65566 is available
with one to four dual redundant 1553 channels on a conduction-
cooled card with an operating temperature of -55° to +85°C,
-40° to +85°C, or 0° to +55°C measured at the rail.
The design of the BU-65566 leverages the field proven
Enhanced Mini-ACE. Each channel may be independently pro-
grammed for BC, RT, Monitor, or RT/Monitor mode.
ENHANCED MINI-ACE
The BU-65566 PMC card incorporates a PCI bridge, along with
between one and four of DDC's Enhanced Mini-ACE hybrid(s).
Each Enhanced Mini-ACE comprises a complete, independent
interface between the PCI bridge and a MIL-STD-1553 bus. The
Enhanced Mini-ACE hybrids provide software compatibility with
DDC's older generation ACE and Mini-ACE (Plus) terminals.
The card provides complete multiprotocol support of MIL-STD-
1553A/B and STANAG 3838. These hybrids include dual trans-
ceivers, along with protocol, host interface, memory manage-
ment logic, and 64K X 16 of RAM with built-in parity checking.
One of the features of the Enhanced Mini-ACE is its enhanced Bus
Controller (BC) architecture. The Enhanced BC's autonomous
message sequence control engine provides a means for offloading
the host processor for implementing multi-frame message sched-
uling, message retry and bus switching schemes, data double
buffering, and asynchronous message insertion. In addition, the
Enhanced BC mode includes 8 general purpose flag bits, a gener-
al purpose queue, and user-defined interrupts, for the purpose of
performing messaging to the host processor. This all serves to
greatly reduce the amount of host processing bandwidth required.
Another important feature of the Enhanced Mini-ACE is the
incorporation of a fully autonomous built-in self-test.
The Enhanced Mini-ACE Remote Terminal (RT) offers the choice
of single, double, and circular buffering for individual subad-
dresses along with a global circular buffering option for multiple
(or all) receive subaddresses, a 50% rollover interrupt for circu-
lar buffers, and an interrupt status queue for logging up to 32
interrupt events. The RT can be configured, via API library to reli-
ably transfer data from RT hardware to a host buffer when one of
these interrupts occurs. The library also allows for the creation of
a user defined Interrupt Service Routine (ISR) on any of the
available interrupts of the Enhanced Mini-ACE.
The transceivers in the Enhanced Mini-ACE series terminals are
fully monolithic, requiring only a +5 volt power input. The transmit-
ters are voltage sources, which provide improved line driving capa-
bility over current sources. This serves to improve performance on
long buses with many taps. The BU-65566's transmitters may be
trimmed to meet the MIL-STD-1760 requirement of a minimum of
20 volts peak-to-peak, transformer coupled (consult factory).
If required, the BU-65566 is also available with an option for
McAir compatible transmitters (consult factory).
FLASH MEMORY
The BU-65566 PMC card includes an 8Mbit (1MB) flash memo-
ry. The flash memory is available to a user (via PCI mapping) for
non-volatile storage. The memory may also be used to store
Enhanced Mini-ACE configuration data. This configuration data
is then used to auto-initialize any or all of the Enhanced Mini-
ACE channels at power-on.
BUILT-IN SELF-TEST
The Enhanced Mini-ACE includes extensive, highly autonomous
self-test capability. This includes both protocol and RAM self-tests.
The Enhanced Mini-ACE protocol test is performed automatically
following power turn-on. In addition, either or both of these self-tests
may be initiated by command(s) from the BU-65566's PCI host. The
API library includes functions to easily perform these tests.
THERMAL DESIGN
The thermal design of this card includes thermal vias located
under the Enhanced Mini-ACE transceiver chips. The transceiver
chips have the highest heat dissipation on the card: 1.22 watts
maximum at 100% transmit duty cycle. Thermally conductive
epoxy in the form of a paste adhesive is applied to the PC board
in the areas under the Enhanced Mini-ACE devices in the Military
(M) version of this card. Heat is conducted through the thermal
vias to an inner copper plane layer, which functions as a heat
spreader. The heat path includes additional thermal vias from the
thermal plane layer to the two copper strips which run the width
of the card (primary thermal interface) and the two copper strips
which run part of the length of the card (secondary thermal inter-
face). Thermal rails from the card base may then be bolted to the
copper strips, providing a path for removing heat from the card.
The BU-65566 “M” card's total thermal resistance, from trans-
ceiver chip junction to the copper strip/thermal rail interface, is 39°
C/W max. This includes the TJC of 11° C/W max for the Enhanced
Mini-ACE hybrid and a thermal resistance of 28°C/W max for the
card, i.e., from the hybrid case to the copper strip/thermal rail
interface. With a rail temperature of 85°C, this results in a maxi-
mum junction temperature of 129°C at 100% transmit duty cycle.
Since the transmit duty cycle for most 1553 BC’s and RT’s is sig-
nificantly less than 100%, this provides ample headroom below
the transceiver chip's maximum junction temperature of 160°C.
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