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參數(shù)資料
| 型號： | BU-65566M19N |
| 廠商： | DATA DEVICE CORP |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 4 CHANNEL(S), MIL-STD-1553 CONTROLLER, XMA64 |
| 文件頁數(shù)： | 9/15頁 |
| 文件大小： | 502K |
| 代理商： | BU-65566M19N |
3
Data Device Corporation
www.ddc-web.com
BU-65566
F-04/06-0
TABLE 1. BU-65566 SPECIFICATIONS
PARAMETER
MIN
TYP
MAX
UNITS
ABSOLUTE MAXIMUM RATINGS
Supply Voltage (Note 9)
+5V
+3.3V (BU-65566MX only)
-0.3
6.0
4.6
V
RECEIVER
Input Impedance, Transformer
Coupled (Notes 1-3)
Threshold Voltage, Transformer
Coupled
Common Mode Voltage (Note 4)
1.000
0.200
0.860
10
Kohm
Vp-p
Vpeak
TRANSMITTER
Differential Output Voltage
Transformer Coupled Across 70
ohms
Output Offset Voltage, Transformer
Coupled Across 70 ohms
Rise/Fall Time
18
-250
100
20
150
27
250
300
Vp-p
mVpeak
ns
POWER SUPPLY REQUIREMENTS
Voltage/Tolerances
+5V
+3.3V (BU-65566MX only)
Current Drain
BU-65566X1
+5V
Idle
50% Duty Transmitter Cycle
100% Duty Transmitter Cycle
+3.3V (BU-65566M1 only)
BU-65566X2
+5V
Idle
50% Duty Transmitter Cycle
100% Duty Transmitter Cycle
+3.3V (BU-65566M2 only)
BU-65566X3
+5V
Idle
50% Duty Transmitter Cycle
100% Duty Transmitter Cycle
+3.3V (BU-65566M3 only)
BU-65566X4
+5V
Idle
50% Duty Transmitter Cycle
100% Duty Transmitter Cycle
+3.3V (BU-65566M4 only)
4.75
3.0
5.0
3.3
250
470
635
355
770
1.091
455
1.076
1.629
550
1.375
2.192
5.5
3.6
280
521
705
80
394
855
1.211
120
505
1.195
1.808
160
611
1.526
2.433
200
V
mA
A
mA
A
mA
A
mA
TABLE 1. BU-65566 SPECIFICATIONS (CONT.)
PARAMETER
MIN
TYP
MAX
UNITS
POWER DISSIPATION (NOTE 9)
BU-65566X1
Idle
50% Duty Transmitter Cycle
100% Duty Transmitter Cycle
BU-65566X2
Idle
50% Duty Transmitter Cycle
100% Duty Transmitter Cycle
BU-65566X3
Idle
50% Duty Transmitter Cycle
100% Duty Transmitter Cycle
BU-65566X4
Idle
50% Duty Transmitter Cycle
100% Duty Transmitter Cycle
1.3
1.6
1.8
2.4
2.7
2.3
3.3
3.9
2.8
4.1
5.4
1.4
1.9
2.1
2.0
2.9
3.3
2.5
3.9
4.8
3.1
4.8
6.6
W
1553 MESSAGE TIMING (CONT)
BC Intermessage Gap - (Note 5)
Non-Enhanced BC mode (Mini-ACE
compatible)
Enhanced BC mode (Note 6)
BC/RT/MT Response Timeout (Note 7)
18.5 nominal
22.5 nominal
50.5 nominal
128.0 nominal
RT Response Time (mid-parity to
mid-sync) (Note 8)
Transmitter Watchdog Timeout
17.5
21.5
49.5
127
4
9.5
10.1
18.5
22.5
50.5
129.5
660.5
19.5
23.5
51.5
131
7
s
THERMAL
Operating Temperature at Thermal Rail
BU-65566MX-900
BU-65566GX-200
BU-65566GX-300
Thermal Resistance
Junction to Thermal Interface “M”
Storage Temperature “M”
“G”
-55
-40
0
-65
+85
+55
+39
+160
+105
°C
°C/W
°C
PHYSICAL CHARACTERISTICS
Size
Weight
BU-65566X1
BU-65566X2
BU-65566X3
BU-65566X4
5.659 x 2.913
(144 x 74)
2.7 (76.5)
3.3 (93.56)
3.9 (110.6)
4.5 (127.6)
in.
(mm)
oz. (g)
MECHANICAL DESIGN
Shock: Three pulses, half sine on six
(6) axes
Vibration: Random input, one hour
each axes 40g’s 11 msec/axes, three
hours total, 15 to 2000 Hz
Resonant Frequency: BU-65566X2
(calculated) 12Hz
40g’s, 11 msec/axes
14g’s rms
12 Hz
TABLE 1 notes:
(Notes 1 through 3 are applicable to the Input Impedance specification:)
(1) The specifications are applicable for both unpowered and powered conditions.
(2) The specifications assume a 2 Volt rms balanced, differential, sinusoidal input.
The applicable frequency is 75 kHz to 1 MHz.
(3) Minimum impedance is guaranteed over the operating range, but is not tested.
(4) Assumes a common mode voltage within the frequency range of dc to 2MHz,
applied to pins of the isolation transformer on the stub side (transformer cou-
pled), and referenced to signal.
(5) Typical value for minimum intermessage gap time. Under software control, this
may be lengthened to 65,535 ms. If ENHANCED CPU ACCESS, bit 14 of
Configuration Register #6, is set to logic “1”, then host accesses during BC Start-
of-Message (SOM) and End-of-Message (EOM) transfer sequences could have
the effect of lengthening the intermessage gap time. For each host access during
an SOM or EOM sequence, the intermessage gap time will be lengthened by 6
clock cycles. Since there are 7 internal transfers during SOM, and 5 during EOM,
this could theoretically lengthen the intermessage gap by up to 72 clock cycles;
i.e., 4.5 s.
(6) For enhanced BC mode, the typical value for intermessage gap time is approx-
imately 625 ns longer than for the non-enhanced BC mode.
(7) Software programmable (4 options). Includes RT-to-RT Timeout (measured mid
parity of transmit Command Word to mid-sync of Transmitting RT Status Word).
(8) Measured from mid-parity crossing of Command Word to mid-sync crossing of
RT’s Status Word.
(9) Power dissipation specifications assume a transformer coupled configuration
with external dissipation (while transmitting) of:
0.14 watts for the active isolation transformer,
0.08 watts for the active bus coupling transformer,
0.45 watts for each of the two bus isolation resistors and
0.15 watts for each of the two bus termination resistors.
(10) All power measurements are for a 33 MHz PCI bus.
1553 MESSAGE TIMING
Completion of CPU Write
(BC Start)-to-Start of Next
Message (Non-enhanced BC
Mode)
2.5
s
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