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參數資料
| 型號： | BU-65743F3-210 |
| 廠商： | DATA DEVICE CORP |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 2 CHANNEL(S), 1M bps, MIL-STD-1553 CONTROLLER, CQFP80 |
| 封裝： | 0.880 INCH, CERAMIC, QFP-80 |
| 文件頁數： | 45/75頁 |
| 文件大?。?/td> | 532K |
| 代理商： | BU-65743F3-210 |
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5
Data Device Corporation
www.ddc-web.com
BU-65743/65843/65863/65864
D-06/04-0
MHz
%
33.3
0.01
0.10
0.001
0.01
-0.01
-0.10
-0.001
-0.01
CLOCK INPUT
PCI CLOCK INPUT FREQUENCY
1553 Clock Frequency
Default Mode
Option
Long Term Tolerance
1553A Compliance
1553B Compliance
Short Term Tolerance, 1 second
1553A Compliance
1553B Compliance
16.0
12.0
10.0
20.0
in.
(mm)
in.
(mm)
Oz.
(g)
in.
(mm)
Oz.
(g)
0.89 X 0.89 X 0.130
(22.6 x 22.6 x 3.3)
MSL-3
1.13
(28.7)
0.4
(10)
0.815 X 0.815 X 0.120
(20.7 x 20.7 x 3.05)
0.088
(2.5)
°C/W
°C
11
12
+100
+150
+300
+125
9
-45
-55
-65
-55
PHYSICAL CHARACTERISTICS
80-Pin, Ceramic Flatpack/Gull Lead
Size, MAXIMUM
Micro-ACE-TE
Moisture Sensitivity Level
Lead Toe-to-Toe Distance
80-Pin Gull Lead, MAXIMUM
Weight
324-ball Plastic BGA
Size, Maximum
Weight
THERMAL
80-Pin, Ceramic Flatpack/Gull Lead
Thermal Resistance, Junction-to-Case,
Hottest Die (
θJC) (Note 12)
324-Ball Plastic BGA
Thermal Resistance,Junction-to-Ball,
Hottest Die (
θJB)
Micro-ACE Temp (case)
Operating Junction Temperature
Storage Temperature
Lead Temperature (soldering, 10 sec.)
CQFP Operating Junction Temp (case)
UNITS
MAX
TYP
MIN
PARAMETER
TABLE 1. PCI MINI-ACE MARK3/MICRO-ACE TE
SPECIFICATIONS (CONT.)
TABLE 1 NOTES:
Notes 1 through 6 are applicable to the Receiver Differential Resistance
and Differential Capacitance specifications:
(1)
Specifications include both transmitter and receiver (tied together
internally).
(2)
Impedance parameters are specified directly between pins TX/RX_A(B)
and TX/RX_A(B) of the PCI Mini-ACE Mark3/PCI Micro-ACE TE hybrid.
(3)
It is assumed that all power and ground inputs to the hybrid are
connected.
(4)
The specifications are applicable for both unpowered and powered
conditions.
(5)
The specifications assume a 2 volt rms balanced, differential, sinu-
soidal input. The applicable frequency range is 75 kHz to 1 MHz.
(6)
Minimum resistance and maximum capacitance parameters are
guaranteed over the operating range, but are not tested.
(7)
Assumes a common mode voltage within the frequency range of dc
to 2 MHz, applied to pins of the isolation transformer on the stub
side (either direct or transformer coupled), and referenced to hybrid
ground. Transformer must be a DDC recommended transformer or
other transformer that provides an equivalent minimum CMRR.
(8)
Typical value for minimum intermessage gap time. Under software
control, this may be lengthened to 65,535 ms - message time, in
increments of 1 s. If ENHANCED CPU ACCESS, bit 14 of
Configuration Register #6, is set to logic "1", then host accesses
during BC Start-of-Message (SOM) and End-of-Message (EOM)
transfer sequences could have the effect of lengthening the inter-
UNITS
MAX
TYP
MIN
PARAMETER
TABLE 1. PCI MINI-ACE MARK3/MICRO-ACE TE
SPECIFICATIONS (CONT.)
s
19.5
23.5
51.5
131
7
2.5
9.5
10.0
to
10.5
18.5
22.5
50.5
129.5
660.5
17.5
21.5
49.5
127
4
1553 MESSAGE TIMING
Completion of CPU Write
(BC Start)-to-Start of First Message
(for Non-enhanced BC Mode)
BC Intermessage Gap (Note 8)
Non-enhanced
(Mini-ACE compatible) BC mode
Enhanced BC mode (Note 9)
BC/RT/MT Response Timeout
(Note 10)
18.5 nominal
22.5 nominal
50.5 nominal
128.0 nominal
RT Response Time
(mid-parity to mid-sync) (Note 11)
Transmitter Watchdog Timeout
message gap time. For each host access during an SOM or EOM
sequence, the intermessage gap time will be lengthened by 6 clock
cycles. Since there are 7 internal transfers during SOM, and 5 dur-
ing EOM, this could theoretically lengthen the intermessage gap by
up to 72 clock cycles; i.e., up to 7.2 s with a 10 MHz clock, 6.0 s
with a 12 MHz clock, 4.5 s with a 16 MHz clock, or 3.6 s with a
20 MHz clock.
(9)
For Enhanced BC mode, the typical value for intermessage gap
time is approximately 10 clock cycles longer than for the non-
enhanced BC mode. That is, an addition of 1.0 s at 10 MHz, 833
ns at 12 MHz, 625 ns at 16 MHz, or 500 ns at 20 MHz.
(10) Software programmable (4 options). Includes RT-to-RT Timeout
(measured mid-parity of transmit Command Word to mid-sync of
transmitting RT Status Word).
(11) Measured from mid-parity crossing of Command Word to mid-sync
crossing of RT's Status Word.
(12)
θJC is measured to the bottom of the case, and the numbers indi-
cated are preliminary
(13) External 10 F Tantalum and 0.1 F capacitors should be located
as close as possible to Pin 10, and a 0.1 F at pins 30, 51 & 69.
(14) MIL-STD-1760 requires that the PCI Mini-ACE Mark3 produce a 20
Vp-p minimum output on the stub connection.
(15) Power dissipation specifications assume a transformer coupled
configuration with external dissipation (while transmitting) of 0.14
watts for the active isolation transformer, 0.80 watts for the active
bus coupling transformer, 0.45 watts for each of the two bus isola-
tion resistors and 0.15 watts for each of the two bus termination
resistors.
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