參數資料
型號: BU21023MUV-E2
廠商: Rohm Semiconductor
文件頁數: 2/22頁
文件大?。?/td> 0K
描述: IC CTLR TOUCH PANEL 28VQFN
特色產品: Resistive Touchscreen Controller Ics
標準包裝: 1
類型: 電阻
觸摸面板接口: 4,2 線
輸入數/鍵: 1 TSC
分辨率(位): 8 b
評估套件: *
數據接口: I²C,串行,SPI?
電源電壓: 1.8V,3V
電流 - 電源: 4mA
工作溫度: -20°C ~ 85°C
安裝類型: 表面貼裝
封裝/外殼: 28-VFQFN 裸露焊盤
供應商設備封裝: 28-QFN
包裝: 標準包裝
其它名稱: BU21023MUV-E2DKR
10
COMMERCIALTEMPERATURERANGE
IDT72V70810 3.3V TIME SLOT INTERCHANGE
DIGITAL SWITCH 1,024 x 1,024
0123
4
5
6
7
8
9
10
11
12
13
14
15
16
ST-BUS Frame
CLK
Offset Value
FE Input
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
GCI Frame
CLK
Offset Value
FE Input
(FD[10:0] = 06H)
(FD11 = 0, sample at CLK LOW phase)
(FD[10:0] = 09H)
(FD11 = 1, sample at CLK HIGH phase)
5710 drw04
TABLE 7 — FRAME ALIGNMENT REGISTER (FAR) BITS
Figure 4. Example for Frame Alignment Measurement
Bit
Name
Description
15-13
Unused
Must be zero for normal operation.
12
CFE
When CFE = 1, the frame evaluation is completed and bits FD10 to FD0 bits contains a valid frame alignment
(Complete Frame Evaluation)
offset. This bit is reset to zero, when SFE bit in the IMS register is changed from 1 to 0.
11
FD11
The falling edge of FE (or rising edge for GCI mode) is sampled during the CLK-high phase (FD11 = 1)
(Frame Delay Bit 11)
or during the CLK-low phase (FD11 = 0). This bit allows the measurement resolution to CLK cycle.
10-0
FD10-0
The binary value expressed in these bits refers to the measured input offset value. These bits are rest to
(Frame Delay Bits)
zero when the SFE bit of the IMS register changes from 1 to 0. (FD10 – MSB, FD0 – LSB)
Read/Write Address:
02H,
Reset Value:
0000H.
15
14
13
12
11
10
9876543210
0
CFE
FD11
FD10
FD9
FD8
FD7
FD6
FD5
FD4
FD3
FD2
FD1
FD0
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