參數(shù)資料
型號(hào): BU2506FV-E2
廠商: Rohm Semiconductor
文件頁(yè)數(shù): 8/13頁(yè)
文件大?。?/td> 0K
描述: IC DAC 10BIT 8-CHAN SSOP20
標(biāo)準(zhǔn)包裝: 1
設(shè)置時(shí)間: 7µs
位數(shù): 10
數(shù)據(jù)接口: 串行
轉(zhuǎn)換器數(shù)目: 8
電壓電源: 單電源
工作溫度: -30°C ~ 85°C
安裝類型: 表面貼裝
封裝/外殼: 20-LSSOP(0.173",4.40mm 寬)
供應(yīng)商設(shè)備封裝: 20-SSOP-B
包裝: 標(biāo)準(zhǔn)包裝
輸出數(shù)目和類型: 8 電壓,單極
采樣率(每秒): *
產(chǎn)品目錄頁(yè)面: 1376 (CN2011-ZH PDF)
其它名稱: BU2506FV-E2DKR
BU2506FV,BU2505FV
Technical Note
4/10
www.rohm.com
2011.04 - Rev.B
2011ROHM Co., Ltd. All rights reserved.
Cascade Connection
A data output terminal for cascade connection (DO) is available for reducing the number of parts when it is increased.
The DO terminal can be connected to a data input terminal (DI) of the next IC.
However, DO transition is synchronized with rising edge of clock signal, DO signal should be delayed, to keep a limit of data hold
time.
For example RC passive filter can be used.
Also in some cases, an operation frequency of logic signal have to be decreased to ensure a margin of data setup time.
Therefore, it is better to control LD port of each LSI separately, if extra CPU ports are available.
In this case, more ports to control LD signals are needed, but a consideration described above doesn’t have do be done.
BU2505FV
BU2506FV
(#2)
BU2505FV
BU2506FV
(#1)
LD
CLK
DI
LD
CLK
DI
LD1
LD2
DI
CLK
BU2505FV
BU2506FV
DO
LD
CLK
DI
(#2)
BU2505FV
BU2506FV
DO
LD
CLK
DI
(#1)
CPU
LD
CLK
DI
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