參數(shù)資料
型號(hào)： BU3081FV
元件分類(lèi)： 時(shí)鐘產(chǎn)生/分配
英文描述： 36.864 MHz, VIDEO CLOCK GENERATOR, PDSO28
封裝： SSOP-28
文件頁(yè)數(shù)： 6/8頁(yè)
文件大?。?/td> 124K
代理商： BU3081FV
BU3081FV
Multimedia ICs
Rev.A
6/7
Electrical characteristics (Unless otherwise noted, VCC=3.3V, Ta=25°C, Crystal frequency=27.0000MHz, No load)
Parameter
Symbol
Min.
Typ.
Max.
Rated value
2.4
0.4
VOH VCLK
VOL VCLK
IDD
IDD2
Output H voltage
Output L voltage
Power supply current
Power supply current2
50
65
100
50
Unit
V
mA
A
Condition
IOH=
4.0mA
IOL= 4.0mA
No load
OE=L
CLK
33.8688
36.864
24.576
22.5792
24.576
16.384
16.9344
18.432
12.288
11.2896
12.288
8.192
MHz
CLK768_44
CLK768_48
CLK768_32
CLK512_44
CLK512_48
CLK512_32
CLK384_44
CLK384_48
CLK384_32
CLK256_44
CLK256_48
CLK256_32
XTAL_IN
(3136 / 625) /4
XTAL_IN
(2048 / 375) /4
XTAL_IN
(4096 / 1125) /4
XTAL_IN
(3136 / 625) /6
XTAL_IN
(2048 / 375) /6
XTAL_IN
(4096 / 1125) /6
XTAL_IN
(3136 / 625) /8
XTAL_IN
(2048 / 375) /8
XTAL_IN
(4096 / 1125) /8
XTAL_IN
(3136 / 625) /12
XTAL_IN
(2048 / 375) /12
XTAL_IN
(4096 / 1125) /12
Note) When input frequency is 27.0000MHz, output frequency is above rated value. Output frequency is
decided by the formula inputted to XTALIN.
Deign guaranteed characteristics
(Unless otherwise noted, VCC=3.3V, Ta=25°C, Crystal frequency=27.0000MHz, No load)
Parameter
Symbol
Min.
Typ.
Max.
Rated value
45
55
300
2.5
50
Unit
Condition
Duty
Jitter 1
σ
Jitter p-p
rise time
fall time
PLL lock time
Duty
JsSD
JsABS
tr
tf
Tlock
1
%
psec
nsec
msec
At 1/2 VDD point
Jitter 1sigma (
1)
MIN-MAX (
1)
Time from 0.2VDD to 0.8VDD
Time from 0.8VDD to 0.2VDD
(
2)
<VCXO>
Frequency variable
range (MAX)
Frequency variable
range (MAX)
(MIN)
+65
155
+110
110
+155
65
ppm
(VCXO_CTRL=0.75VDD)
(VCXO_CTRL=0.25VDD)
<VCO>
(MIN)
27.675
22
30
24
32
26.325
MHz
(VCO_CTRL=0.75VDD)
(VCO_CTRL=0.25VDD)
Note 2) However, it is just the guarantee of IC and dispersion of X'tal and so on is not taken in consideration.
(
1) JITTER means center value when using Time Interval Analyzer with 10,000 sampling.
(
2) Time between voltage supply leads to 3.0V and output clock gets stable.
Switching
VIDEO_SEL input
VCXO output
EXT_IN1
VCLK_OUT
VCXO output
Output L
EXT_IN1
VCXO output
1
2
1
2
1
2
After VIDEO_SEL was switched, when VIDEO_SEL is switched again before VCLK_OUT is switched, less than half clock may be output in VCLK_OUT.
(Operation of VCLK_OUT at the time of VIDEO_SEL input switching)
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