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參數(shù)資料
| 型號(hào)： | BU4815F-TR |
| 元件分類(lèi)： | 電源管理 |
| 英文描述： | 1-CHANNEL POWER SUPPLY SUPPORT CKT, PDSO4 |
| 封裝： | ROHS COMPLIANT, SOP-4 |
| 文件頁(yè)數(shù)： | 5/9頁(yè) |
| 文件大?。?/td> | 277K |
| 代理商： | BU4815F-TR |
Technical Note
5/8
BU48□□G Series, BU48□□F Series, BU48□□FVE Series,
BU49□□G Series, BU49□□F Series, BU49□□FVE Series
www.rohm.com
2011.03 - Rev.D
2011 ROHM Co., Ltd. All rights reserved.
●
Reference Data
Examples of Output rising value(TPLH)and Output falling value(TPHL)
Part Number
TPLH[s]
TPHL[s]
BU4845G/F/FVE
23.3
275.9
BU4945G/F/FVE
3.5
354.3
VDD=4.3V5.1V
VDD=5.1V4.3V
* This data is for reference only.
This figure will vary with the application, so please confirm actual operation conditions before use.
●
Explanation of Operation
For both the open drain type(Fig.12)and the CMOS output type(Fig.13), the detection and release voltages are used as
threshold voltages. When the voltage applied to the VDD pins reaches the applicable threshold voltage, the Vout terminal
voltage switches from either “High” to “Low” or from “Low” to “High”. Because the BU48□□G/F/FVE series uses an open
drain output type, it is possible to connect a pull-up resistor to VDD or another power supply [The output “High” voltage
(VOUT) in this case becomes VDD or the voltage of the other power supply].
Fig.12 (BU48□□ type internal block diagram)
Fig.13 (BU49□□ type internal block diagram)
●
Timing Waveforms
Example:The following shows the relationship between the input voltage VDD, the CT Terminal Voltage VCT and the output
voltage VOUT when the input power supply voltage VDD is made to sweep up and sweep down (The circuits are those in
Fig.12 and 13).
①
When the power supply is turned on, the output is unsettled
from after over the operating limit voltage (VOPL) until TPHL.
Therefore it is possible that the reset signal is not outputted
when the rise time of VDD is faster than TPHL.
②
When VDD is greater than VOPL but less than the reset release
voltage (VDET + VDET), output (VOUT) voltages will switch to L.
③
If VDD exceeds the reset release voltage (VDET + VDET), then
VOUT switches from L to H (with a delay of TPLH).
④
If VDD drops below the detection voltage (VDET) when the
power supply is powered down or when there is a power
supply fluctuation, VOUT switches to L (with a delay of TPHL).
⑤
The potential deference between the detection voltage and the
release voltage is known as the hysteresis width (VDET). The
system is designed such that the output does not flip-flop with
power supply fluctuations within this hysteresis width,
preventing malfunctions due to noise.
Q1
Vref
R1
R2
R3
VOUT
VDD
GND
RL
VDD
RESET
Q2
Q1
Vref
R1
R2
R3
VOUT
VDD
GND
RESET
VDD
VDET+ΔVDET
VDET
VOPL
0V
TPHL
①
②
VOUT
TPLH
TPHL
TPLH
③
④
VOL
VOH
⑤
Fig.14
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