參數(shù)資料
型號: BU7346GUL
元件分類: 時鐘產(chǎn)生/分配
英文描述: 38 MHz, OTHER CLOCK GENERATOR, PBGA6
文件頁數(shù): 3/5頁
文件大?。?/td> 130K
代理商: BU7346GUL
3/4
REV. A
A3: PDB
VDD=3.3V, Ta=25℃, XIN=27.0000MHz
38.0000MHz output (OUT=XIN×(76/27)/2) as SEL=L
36.0000MHz output (OUT=XIN×(8/3)/2) as SEL=H
●Cautions on use(BU7346GUL)
Basically, mount ICs to the printed circuit board for use. (If the ICs are not mounted to the printed circuit board, the
characteristics of ICs may not be fully demonstrated.)
Mount 0.1
F capacitors in the vicinity of the IC PINs between B1 PIN(VDD) and B2 PIN(VSS), respectively.
Depending on the conditions of the printed circuit board, mount an additional electrolytic capacitor between the
power supply and GND terminal.
For EMI protection, it is effective to put ferrite beads in the origin of power supply to be fed to BU7346GUL from the
printed circuit board or to insert a capacitor (of 1
or less), which bypasses high frequency desired, between the
power supply and the GND terminal.
When power is first supplied to the CMOS IC, it is possible that the internal logic may be unstable and rush current
may flow instantaneously. Therefore, give special consideration to power coupling capacitance, power wiring, width
of GND wiring, and routing of connections.
PIN No.
PIN
NAME
Function
A1
XIN
Clock input pin (27.0000MHz input)
A2
SEL
SEL pin (L:38.0000MHz, H:36.0000MHz),
Equipment with pull-down function (Typ.100k
)
A3
PDB
Power down (L:disable, H:enable),
Equipment with pull-down function (Typ.100k
)
Output fixed to L at disable
B1
VDD
Power supply
B2
VSS
GND
B3
OUT
Clock output terminal
(SEL=L:38.0000MHz, SEL=H:36.0000MHz)
A1: XIN
B1: VDD
B2: VSS
B3: OUT
A2: SEL
PLL
1/2
DATA1
DATA2
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