參數(shù)資料
型號(hào): BW1220X
英文描述: Rad hard low voltage CMOS 16-bit bus buffer transceiver (3-state) with 3.6 V tolerant inputs and outputs
中文描述: BW1220X CCD信號(hào)處理器的攝像BW1220X |數(shù)據(jù)資料
文件頁(yè)數(shù): 2/11頁(yè)
文件大?。?/td> 140K
代理商: BW1220X
BW1223X
8BIT 40MSPS ADC
SEC ASIC
ANALOG
CORE
PIN
DESCRIPTION
NAME
I/O TYPE
I/O PAD
PIN DESCRIPTION
VRTS
AB
poa_bb
Internal Reference Top Bias
(Short to VRTS for Self-Bias)
VRT
AB
poa_bb
2.6V External Reference Top Bias
VRBS
AB
poa_bb
Internal Reference Bottom Bias
(Short to VRBS for Self-Bias)
VRB
AB
poa_bb
0.6V External Reference Bottom Bias
VDDA
AP
vdda
+3.3V Analog Power.
VBBA
AG
vbba
Analog Sub Bias.
VSSA
AG
vssa
Analog Ground.
AIN
AI
piar10_bb
Analog Input
Input Span : VRB ~ VRT
CLK
DI
picc_bb
Clock Input
DO[7:0]
DO
pot2_bb
Digital Output
VBBD
DG
vbba
Digital Sub Bias.
VSSD
DG
vsstd
Digital Ground.
VDDD
DP
vddd
Digital Power.
CORE
CONFIGURATION
AIN
VRTS
VRBS
CLK
DO[0] (LSB)
DO[7] (MSB)
DO[1]
DO[2]
DO[3]
DO[4]
DO[5]
DO[6]
VRT
VRB
bw1223x
VDDA VSSA VBBAVDDD VSSD VBBD
I/O TYPE ABBR.
AI : Analog Input
DI : Digital Input
AO : Analog Output
DO : Digital Output
AB : Analog Bidirectional
DB : Digital Bidirectional
AP : Analog Power
DP : Digital Power
AG : Analog Ground
DG : Digital Ground
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相關(guān)PDF資料
PDF描述
BW1221L Rad hard low voltage CMOS 16-bit bus buffer transceiver (3-state) with 3.6 V tolerant inputs and outputs
BW1221L_2CLK Rad hard low voltage CMOS 16-bit bus buffer transceiver (3-state) with 3.6 V tolerant inputs and outputs
BW1221L_3CLK Rad hard low voltage CMOS 16-bit bus buffer transceiver (3-state) with 3.6 V tolerant inputs and outputs
BW1222L Rad hard low voltage CMOS 16-bit D-type latch (3-state) with 3.6 V tolerant inputs and outputs
BW1237X Rad hard low voltage CMOS 16-bit D-type Flip-Flop (3-state) with 3.6 V tolerant inputs and outputs
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