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參數(shù)資料
| 型號(hào)： | BW1249X |
| 英文描述： | Rad hard low voltage CMOS 16-bit bus buffer transceiver (3-state) with 3.6 V tolerant inputs and outputs |
| 中文描述： | BW1249X 4-14位40MSPS單援BW1249X |數(shù)據(jù)資料 |
| 文件頁(yè)數(shù)： | 10/12頁(yè) |
| 文件大?。?/td> | 77K |
| 代理商： | BW1249X |
SEC ASIC
BW1244D
3.3V 10BIT 0.5MSPS DAC
ANALOG
PC BOARD LAYOUT CONSIDERATION
1. PC Board Considerations
To minimize noise on the power lines and the ground lines, the digital inputs
need to be shielded and decoupled. This trace length between groups
of VDD (VDDA,VDDD) and VSS (VSSA,VSSD) pins should be as short as possible
so as to minimize inductive ringing.
2. Supply Decoupling and Planes
For the decoupling capacitor between the power line and the ground line, 0.1uF
ceramic capacitor is used in parallel with a 10uF tantalum capacitor.
The digital power plane(VDDD) and analog power plane(VDDA) are connected
through a ferrite bead, and also the digital ground plane(VSSD) and the analog
ground plane(VSSA). This ferrite bead should be located within 3inches of
the BW1244D. The analog power plane supplies power to the BW1244D of
the analog output pin and related devices.
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