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參數(shù)資料
| 型號： | BW1249X |
| 英文描述： | Rad hard low voltage CMOS 16-bit bus buffer transceiver (3-state) with 3.6 V tolerant inputs and outputs |
| 中文描述： | BW1249X 4-14位40MSPS單援BW1249X |數(shù)據資料 |
| 文件頁數(shù)： | 5/12頁 |
| 文件大?。?/td> | 77K |
| 代理商： | BW1249X |
SEC ASIC
BW1244D
3.3V 10BIT 0.5MSPS DAC
ANALOG
TIMING DIAGRAM
1. Output delay measured from the 50% point of the rising edge of input data to the full scale transition.
2. Settling time measured from the 50% point of full scale transition to the output remaining within ±1/2 LSB.
3. Output rise/fall time measured between the 10% and 90% points of full scale transition.
FUNCTIONAL DESCRIPTION
1. The bw1244d has a R-2R Ladder Block for 10bit and an OP amp Block for driving Output.
2. The R-2R Ladder Block generates binary weighted voltage (VRT/2
1
, VRT/2
2
, VRT/2
3
, …VRT/2
10
)
corresponding to Digital Input Data for n-bit DAC and Output total voltage is summing of each values.
3. In Output voltage,
V
MSB
= VRT/2
1
V
LSB
= VRT/2
10
4. Output of the R-2R Ladder Block is driven by OP amp.
5. The DACCON signal controls OP amp input. When DACCON is low, the bw1244d operates normally
so R-2R Ladder output drives OP amp input But when DACCON is high, OP amp input is connected to
EXTREF, so bw1244d output is buffered signal of EXTREF.
6. In power down mode, only analog current (I
VDDA
) is reduced.
DATA
VOUT
Td
0000000000
1111111111
50%
50%
VOUT
0000000000
1111111111
0000000000
10%
90%
DATA
Tr
Tf
VOUT
0000000000
1111111111
0000000000
±
0.5LSB
50%
DATA
Ts
PWRDN
VOUT
Ton
50%
Toff
50%
±
0.5LSB
±
0.5LSB
0.0V
5 / 11
DACCON
VOUT
Texon
50%
Texoff
50%
±
0.5LSB
±
0.5LSB
EXTREF
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