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參數(shù)資料
| 型號(hào)： | BW1254X |
| 英文描述： | Rad hard low voltage CMOS 16-bit bus buffer transceiver (3-state) with 3.6 V tolerant inputs and outputs |
| 中文描述： | BW1254X 4-14高達(dá)10MSPS模數(shù)轉(zhuǎn)換器BW1254X |數(shù)據(jù)資料 |
| 文件頁(yè)數(shù)： | 6/13頁(yè) |
| 文件大?。?/td> | 140K |
| 代理商： | BW1254X |
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SEC ASIC
BW1251X
12bit 500KSPS ADC
MIXED
TIMING DIAGRAM
1. Main Waveform
2. STC & CKIN Condition
The A/D Converter operates data conversion when STC (Start Conversion) signal is just "HIGH". Otherwise,
output data (DO[11:0]) keep the current states. The STC signal should be changed during "T
SAFE
" with the
"HIGH" level of
the clock to operation as shown in the main waveform.
·
ADC External Interface Signal
AINT : Analog Input Signal (Input)
Input Range : VREF ~ AGND
STBY : Stand-by Signal, Power Save Mode (Input)
CKIN : ADC Main Clock, f
CKIN
= 2.5MHz, 1 Clock Period = 400ns (Input)
STC
: Start of Conversion Signal (Input)
EOC
: End of Conversion Signal (Output)
DO[11:0] : Digital Output Signal (Output)
STBY
STC
DO[11:0]
1
CKIN
Input Sampling Period
2
AINT
A1
EOC
3
4
5
A2
10ns
3ns
T
SAFE
CKIN
STC
6/12
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