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參數(shù)資料
| 型號(hào)： | BW2006L |
| 英文描述： | Rad-hard quad 2-input NAND gate |
| 中文描述： | BW2006L 100MHz的?500MHz的FSPLL BW2006L |數(shù)據(jù)資料 |
| 文件頁數(shù)： | 5/8頁 |
| 文件大?。?/td> | 814K |
| 代理商： | BW2006L |
100MHz~500MHz FSPLL
BW2006L
CORE EVALUATION GUIDE
NOTES
: 10uF ELECTROLYTIC CAPACITOR
UNLESS OTHERWISE SPECIFIED
: 103 CERAMIC CAPACITOR
UNLESS OTHERWISE SPECIFIED
FOUT
FILTER
BW2006L
#1.14bit Register Block
PWRDN
P<5:0>
S<1:0>
300pF
M<5:0>
FIN
External
Source
Clock
VDD
VSS
VDDA VSSA
3.3V Digital Power
3.3V Analog Power
GND
GND
VSSA
Select Pin
Test Pins of N Sample bits
(used to primary pad cells)
Internal Divider Signal Line
#2
M
U
X
For the embedded PLL, we must consider the test circuits for the embedded PLL core in multiple
applications.
Hence, the following requirements should be satisfied.
- The FILTER and FOUT pins must be provided for test.
- For PLL test (Below 2 examples),
it is needed to control the dividers - M<5:0>,P<5:0> and S<1:0> -that generate multiple clocks.
#1. Registers can be used for easy control of divider values.
#2. N sample bits of 14-bit divider pins can be bypassed for test using MUX.
Figure3 . Core
evaluation
guide
VBB
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