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參數(shù)資料
| 型號(hào)： | BW2006L |
| 英文描述： | Rad-hard quad 2-input NAND gate |
| 中文描述： | BW2006L 100MHz的?500MHz的FSPLL BW2006L |數(shù)據(jù)資料 |
| 文件頁(yè)數(shù)： | 7/8頁(yè) |
| 文件大?。?/td> | 814K |
| 代理商： | BW2006L |
100MHz~500MHz FSPLL
BW2006L
Design Considerations
The following design considerations are applied :
* Phase tolerance and jitter are independent of the PLL frequency.
* Jitter is affected by the noise frequency in the power(VDD/VSS,VDDA/VSSA/VSUB and VBB) .
It increases when noise level increases.
* A CMOS-level input reference clock is recommended for signal compatibility with the PLL circuit.
Other levels such as TTL may degrade the tolerances.
* The use of two, or more PLLs requires special design considerations. Please consult your application
engineer for more information.
* The following apply to the noise level, which can be minimized by using good analog power and
ground isolation techniques in the system:
- Use wide PCB traces for POWER(VDD/VSS, VDDA/VSSA/VSUB and VBB) connections to the
PLL core.
Seperate the traces from the chip's VDD/VSS,VDDA/VSSA/VSUB and VBB supplies.
- Use proper VDD/VSS,VDDA/VSSA/VSUB and VBB decoupling.
- Use good power and ground sources on the board .
- Use Power VBB(=VSUB) to minimize substrate noise.
* The PLL core should be placed as close as possible to the dedicated loop filter and analog
Power and ground pins.
* It is inadvisable to locate noise-generating signals, such as data busses and high-current outputs,
near the PLL I/O cells.
* Other related I/O signals should be placed near the PLL I/O but do not have any pre-defined
placement restriction.
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