參數(shù)資料
型號: BX805555080A
廠商: INTEL CORP
元件分類: 微控制器/微處理器
英文描述: 64-BIT, MICROPROCESSOR, BGA771
封裝: LGA-771
文件頁數(shù): 20/104頁
文件大?。?/td> 3690K
代理商: BX805555080A
Electrical Specifications
22
Dual-Core Intel Xeon Processor 5000 Series Datasheet
With the implementation of a source synchronous data bus comes the need to specify
two sets of timing parameters. One set is for common clock signals whose timings are
specified with respect to rising edge of BCLK0 (ADS#, HIT#, HITM#, and so forth) and
the second set is for the source synchronous signals which are relative to their
respective strobe lines (data and address) as well as rising edge of BCLK0.
Asynchronous signals are still present (A20M#, IGNNE#, and so forth) and can become
active at any time during the clock cycle. Table 2-6 identifies which signals are common
clock, source synchronous and asynchronous.
Notes:
1.
Refer to Section 5 for signal descriptions.
2.
These signals may be driven simultaneously by multiple agents (Wired-OR).
Table 2-6.
FSB Signal Groups
Signal Group
Type
Signals1
AGTL+ Common Clock Input
Synchronous to BCLK[1:0]
BPRI#, DEFER#, RESET#, RS[2:0]#, RSP#,
TRDY#
AGTL+ Common Clock I/O
Synchronous to BCLK[1:0]
ADS#, AP[1:0]#, BINIT#2, BNR#2,
BPM[5:0]#, BR[1:0]#, DBSY#, DP[3:0]#,
DRDY#, HIT#2, HITM#2, LOCK#, MCERR#2
AGTL+ Source Synchronous I/O
Synchronous to assoc.
strobe
AGTL+ Strobes I/O
Synchronous to BCLK[1:0]
ADSTB[1:0]#, DSTBP[3:0]#, DSTBN[3:0]#
AGTL+ Asynchronous Output
Asynchronous
FERR#/PBE#, IERR#, PROCHOT#
GTL+ Asynchronous Input
Asynchronous
A20M#, FORCEPR#, IGNNE#, INIT#, LINT0/
INTR, LINT1/NMI, SMI#, STPCLK#
GTL+ Asynchronous Output
Asynchronous
THERMTRIP#
FSB Clock
Clock
BCLK1, BCLK0
TAP Input
Synchronous to TCK
TCK, TDI, TMS TRST#
TAP Output
Synchronous to TCK
TDO
Power/Other
BSEL[2:0], COMP[7:0], GTLREF_ADD_C[1:0],
GTLREF_DATA_C[1:0], LL_ID[1:0],
MS_ID[1:0], PWRGOOD, Reserved, SKTOCC#,
TEST_BUS, TESTHI[11:0], THERMDA,
THEMRDA2, THERMDC, THERMDC2, VCC, VCCA,
VCCIOPLL, VCC_DIE_SENSE, VCC_DIE_SENSE2,
VID[5:0], VID_SELECT, VSS_DIE_SENSE,
VSS_DIE_SENSE2, VSS, VSSA, VTT, VTTOUT,
VTTPWRGD
Signals
Associated Strobe
REQ[4:0]#,A[16:3]
#
ADSTB0#
A[35:17]#
ADSTB1#
D[15:0]#, DBI0#
DSTBP0#, DSTBN0#
D[31:16]#, DBI1#
DSTBP1#, DSTBN1#
D[47:32]#, DBI2#
DSTBP2#, DSTBN2#
D[63:48]#, DBI3#
DSTBP3#, DSTBN3#
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