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參數(shù)資料
| 型號： | C164CL |
| 廠商： | INFINEON TECHNOLOGIES AG |
| 英文描述： | 16-Bit Single-Chip Microcontroller |
| 中文描述： | 16位單片機 |
| 文件頁數(shù)： | 33/79頁 |
| 文件大?。?/td> | 1314K |
| 代理商： | C164CL |
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C164CI/SI
C164CL/SL
Data Sheet
29
V2.0, 2001-05
Oscillator Watchdog
The Oscillator Watchdog (OWD) monitors the clock signal generated by the on-chip
oscillator (either with a crystal or via external clock drive). For this operation the PLL
provides a clock signal which is used to supervise transitions on the oscillator clock. This
PLL clock is independent from the XTAL1 clock. When the expected oscillator clock
transitions are missing the OWD activates the PLL Unlock/OWD interrupt node and
supplies the CPU with the PLL clock signal. Under these circumstances the PLL will
oscillate with its basic frequency.
In direct drive mode the PLL base frequency is used directly (
f
CPU
= 2
…
5 MHz).
In prescaler mode the PLL base frequency is divided by 2 (
f
CPU
= 1
…
2.5 MHz).
Note: The CPU clock source is only switched back to the oscillator clock after a
hardware reset.
The oscillator watchdog can be disabled
by setting bit OWDDIS in register SYSCON.
In this case (OWDDIS =
‘
1
’
) the PLL remains idle and provides no clock signal, while the
CPU clock signal is derived directly from the oscillator clock or via prescaler or SDD. Also
no interrupt request will be generated in case of a missing oscillator clock.
Note: At the end of a reset bit OWDDIS reflects the inverted level of pin RD at that time.
Thus the oscillator watchdog may also be disabled via hardware by (externally)
pulling the RD line low upon a reset, similar to the standard reset configuration via
PORT0.
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| C164SM | 16-Bit Single-Chip Microcontrol ler |
| C164SV | 16-Bit Single-Chip Microcontroller |
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