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參數資料
| 型號： | C509-L |
| 廠商： | SIEMENS AG |
| 元件分類： | 8位微控制器 |
| 英文描述： | 8-Bit CMOS Microcontroller |
| 中文描述： | 8位CMOS微控制器 |
| 文件頁數： | 61/74頁 |
| 文件大?。?/td> | 1607K |
| 代理商： | C509-L |
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C509-L
Semiconductor Group
60
Fail Save Mechanisms
The C509-L offers two on-chip peripherals which monitor the program flow and ensure an automatic
"fail-safe" reaction for cases where the controller’s hardware fails or the software hangs up:
– A programmable watchdog timer (WDT) with variable time-out period from 189 microseconds
up to approx. 0.79 seconds at 16 MHz.
– An oscillator watchdog (OWD) which monitors the on-chip oscillator and forces the
microcontroller into the reset state if the on-chip oscillator fails.
Programmable Watchdog Timer
The watchdog timer in the C509-L is a 15-bit timer, which is incremented by a count rate of
f
OSC
/12
up to
f
OSC
/384. For programming of the watchdog timer overflow rate, the upper 7 bit of the watchdog
timer can be written.
Figure 34
shows the block diagram of the watchdog timer unit.
Figure 34
Block Diagram of the Programmable Watchdog Timer
The watchdog timer can be started by software (bit SWDT) or by hardware through pin PE/SWD,
but it cannot be stopped during active mode of the C509-L. If the software fails to refresh the running
watchdog timer an internal reset will be initiated on watchdog timer overflow. For refreshing of the
watchdog timer the content of the SFR WDTREL is transferred to the upper 7-bit of the watchdog
timer. The refresh sequence consists of two consecutive instructions which set the bits WDT and
SWDT each. The reset cause (external reset or reset caused by the watchdog) can be examined
by software (flag WDTS). It must be noted, however, that the watchdog timer is halted during the
idle mode and power down mode of the processor.
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