參數(shù)資料
型號: C8051F002R
廠商: Silicon Laboratories Inc
文件頁數(shù): 36/171頁
文件大小: 0K
描述: IC 8051 MCU 32K FLASH 32LQFP
標準包裝: 1
系列: C8051F00x
核心處理器: 8051
芯體尺寸: 8-位
速度: 20MHz
連通性: SMBus(2 線/I²C),SPI,UART/USART
外圍設備: 欠壓檢測/復位,POR,PWM,溫度傳感器,WDT
輸入/輸出數(shù): 8
程序存儲器容量: 32KB(32K x 8)
程序存儲器類型: 閃存
RAM 容量: 256 x 8
電壓 - 電源 (Vcc/Vdd): 2.7 V ~ 3.6 V
數(shù)據(jù)轉(zhuǎn)換器: A/D 4x12b; D/A 2x12b
振蕩器型: 內(nèi)部
工作溫度: -40°C ~ 85°C
封裝/外殼: 32-LQFP
包裝: 剪切帶 (CT)
其它名稱: 336-1002-1
C8051F000/1/2/5/6/7
C8051F010/1/2/5/6/7
18. UART
The UART is a serial port capable of asynchronous transmission. The UART can function in full duplex mode. In
all modes, receive data is buffered in a holding register. This allows the UART to start reception of a second
incoming data byte before software has finished reading the previous data byte.
The UART has an associated Serial Control Register (SCON) and a Serial Data Buffer (SBUF) in the SFRs. The
single SBUF location provides access to both transmit and receive registers. Reads access the Receive register and
writes access the Transmit register automatically.
The UART is capable of generating interrupts if enabled. The UART has two sources of interrupts: a Transmit
Interrupt flag, TI (SCON.1) set when transmission of a data byte is complete, and a Receive Interrupt flag, RI
(SCON.0) set when reception of a data byte is complete. The UART interrupt flags are not cleared by hardware
when the CPU vectors to the interrupt service routine. They must be cleared manually by software. This allows
software to determine the cause of the UART interrupt (transmit complete or receive complete).
Figure 18.1. UART Block Diagram
SBUF
Shift
Load SBUF
SFR Bus
Input Shift Register
(9 bits)
Bit Detector
Read
SBUF
Rx Control
Start
Rx Clock
Load
SBUF
0x1FF
Shift
Tx Control
Tx Clock
Serial
Port
Interrupt
Tx IRQ
Zero Detector
Send
Shift
SBUF
SFR Bus
SET
Q
D
CLR
Stop Bit
Gen.
TB8
Start
01
00
10
11
SMOD
1
0
01
00
10
11
Timer 2
Overflow
TCLK
1
0
RCLK
1
0
Timer 1
Overflow
SCON
S
M
2
T
B
8
R
B
8
T
I
R
I
PCON
S
M
O
D
SMOD
Data
Write to
SBUF
S
M
1
S
M
0
R
E
N
Enable
REN
T2CON
R
C
L
K
T
C
L
K
SYSCLK
MSB
RB8
Rx IRQ
TI
RI
Crossbar
Baud Rate Generation Logic
Crossbar
RX
TX
Port I/O
1
0
32
64
12
SM0, SM1
{MODE}
16
2
Rev. 1.7
130
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