參數(shù)資料
型號(hào): C8051F002R
廠商: Silicon Laboratories Inc
文件頁數(shù): 7/171頁
文件大小: 0K
描述: IC 8051 MCU 32K FLASH 32LQFP
標(biāo)準(zhǔn)包裝: 1
系列: C8051F00x
核心處理器: 8051
芯體尺寸: 8-位
速度: 20MHz
連通性: SMBus(2 線/I²C),SPI,UART/USART
外圍設(shè)備: 欠壓檢測(cè)/復(fù)位,POR,PWM,溫度傳感器,WDT
輸入/輸出數(shù): 8
程序存儲(chǔ)器容量: 32KB(32K x 8)
程序存儲(chǔ)器類型: 閃存
RAM 容量: 256 x 8
電壓 - 電源 (Vcc/Vdd): 2.7 V ~ 3.6 V
數(shù)據(jù)轉(zhuǎn)換器: A/D 4x12b; D/A 2x12b
振蕩器型: 內(nèi)部
工作溫度: -40°C ~ 85°C
封裝/外殼: 32-LQFP
包裝: 剪切帶 (CT)
其它名稱: 336-1002-1
C8051F000/1/2/5/6/7
C8051F010/1/2/5/6/7
not affect the push-pull Port I/O. Furthermore, the weak pullup is turned off on an open-drain output that is driving
a 0 to avoid unnecessary power dissipation.
The third and final step is to initialize the individual resources selected using the appropriate setup registers.
Initialization procedures for the various digital resources may be found in the detailed explanation of each available
function. The reset state of each register is shown in the figures that describe each individual register.
Figure 15.1. Port I/O Functional Block Diagram
XBR0, XBR1,
XBR2 Registers
PRT3CF
Register
External
Pins
P0
P1
P2
8
(Internal
Digital
Signals)
Port
Latches
P3
I/O
Cells
P3.0
Digital
Crossbar
Priority
Decoder
P1
I/O
Cells
SMBus
SPI
UART
PCA
T0, T1, T2,
T2EX,
/INT0,
/INT1
/SYSCLK
CNVSTR
P3.7
P1.0
P1.7
P2
I/O
Cells
P2.0
P2.7
P0
I/O
Cells
P0.0
P0.7
8
Highest
Priority
Lowest
Priority
Highest
Priority
Lowest
Priority
8
(P2.0-P2.7)
(P1.0-P1.7)
(P0.0-P0.7)
8
PRT0CF, PRT1CF,
PRT2CF Registers
(P3.0-P3.7)
Comptr.
Outputs
2
4
2
6
2
6
Figure 15.2. Port I/O Cell Block Diagram
DGND
/PORT-OUTENABLE
PORT-OUTPUT
PORT-INPUT
PUSH-PULL
VDD
WEAKPUD
PORT
PAD
(WEAK)
Rev. 1.7
104
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