參數(shù)資料
型號(hào): C8051F005
廠商: Silicon Laboratories Inc
文件頁數(shù): 149/171頁
文件大小: 0K
描述: IC 8051 MCU 32K FLASH 64TQFP
標(biāo)準(zhǔn)包裝: 160
系列: C8051F00x
核心處理器: 8051
芯體尺寸: 8-位
速度: 25MHz
連通性: SMBus(2 線/I²C),SPI,UART/USART
外圍設(shè)備: 欠壓檢測(cè)/復(fù)位,POR,PWM,溫度傳感器,WDT
輸入/輸出數(shù): 32
程序存儲(chǔ)器容量: 32KB(32K x 8)
程序存儲(chǔ)器類型: 閃存
RAM 容量: 2.25K x 8
電壓 - 電源 (Vcc/Vdd): 2.7 V ~ 3.6 V
數(shù)據(jù)轉(zhuǎn)換器: A/D 8x12b,D/A 2x12b
振蕩器型: 內(nèi)部
工作溫度: -40°C ~ 85°C
封裝/外殼: 64-TQFP
包裝: 托盤
C8051F000/1/2/5/6/7
C8051F010/1/2/5/6/7
10.4.5. Interrupt Register Descriptions
The SFRs used to enable the interrupt sources and set their priority level are described below. Refer to the datasheet
section associated with a particular on-chip peripheral for information regarding valid interrupt conditions for the
peripheral and the behavior of its interrupt-pending flag(s).
Figure 10.9. IE: Interrupt Enable
R/W
Reset Value
EA
IEGF0
ET2
ES
ET1
EX1
ET0
EX0
00000000
Bit7
Bit6
Bit5
Bit4
Bit3
Bit2
Bit1
Bit0
SFR Address:
(bit addressable)
0xA8
Bit7:
EA: Enable All Interrupts.
This bit globally enables/disables all interrupts. It overrides the individual interrupt mask
settings.
0: Disable all interrupt sources.
1: Enable each interrupt according to its individual mask setting.
Bit6:
IEGF0: General Purpose Flag 0.
This is a general purpose flag for use under software control.
Bit5:
ET2: Enable Timer 2 Interrupt.
This bit sets the masking of the Timer 2 interrupt.
0: Disable all Timer 2 interrupts.
1: Enable interrupt requests generated by the TF2 flag (T2CON.7)
Bit4:
ES: Enable Serial Port (UART) Interrupt.
This bit sets the masking of the Serial Port (UART) interrupt.
0: Disable all UART interrupts.
1: Enable interrupt requests generated by the R1 flag (SCON.0) or T1 flag (SCON.1).
Bit3:
ET1: Enable Timer 1 Interrupt.
This bit sets the masking of the Timer 1 interrupt.
0: Disable all Timer 1 interrupts.
1: Enable interrupt requests generated by the TF1 flag (TCON.7).
Bit2:
EX1: Enable External Interrupt 1.
This bit sets the masking of external interrupt 1.
0: Disable external interrupt 1.
1: Enable interrupt requests generated by the /INT1 pin.
Bit1:
ET0: Enable Timer 0 Interrupt.
This bit sets the masking of the Timer 0 interrupt.
0: Disable all Timer 0 interrupts.
1: Enable interrupt requests generated by the TF0 flag (TCON.5).
Bit0:
EX0: Enable External Interrupt 0.
This bit sets the masking of external interrupt 0.
0: Disable external interrupt 0.
1: Enable interrupt requests generated by the /INT0 pin.
79
Rev. 1.7
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參數(shù)描述
C8051F005/0046 制造商:Silicon Laboratories Inc 功能描述:
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