參數(shù)資料
型號(hào): C8051F010
廠商: Silicon Laboratories Inc
文件頁數(shù): 63/171頁
文件大?。?/td> 0K
描述: IC 8051 MCU 32K FLASH 64TQFP
標(biāo)準(zhǔn)包裝: 160
系列: C8051F01x
核心處理器: 8051
芯體尺寸: 8-位
速度: 20MHz
連通性: SMBus(2 線/I²C),SPI,UART/USART
外圍設(shè)備: 欠壓檢測(cè)/復(fù)位,POR,PWM,溫度傳感器,WDT
輸入/輸出數(shù): 32
程序存儲(chǔ)器容量: 32KB(32K x 8)
程序存儲(chǔ)器類型: 閃存
RAM 容量: 256 x 8
電壓 - 電源 (Vcc/Vdd): 2.7 V ~ 3.6 V
數(shù)據(jù)轉(zhuǎn)換器: A/D 8x10b; D/A 2x12b
振蕩器型: 內(nèi)部
工作溫度: -40°C ~ 85°C
封裝/外殼: 64-TQFP
包裝: 托盤
C8051F000/1/2/5/6/7
C8051F010/1/2/5/6/7
20.1.
Capture/Compare Modules
Each module can be configured to operate independently in one of four operation modes: Edge-triggered Capture,
Software Timer, High Speed Output, or Pulse Width Modulator. Each module has Special Function Registers
(SFRs) associated with it in the CIP-51 system controller. These registers are used to exchange data with a module
and configure the module’s mode of operation.
Table 20.1 summarizes the bit settings in the PCA0CPMn registers used to place the PCA capture/compare modules
into different operating modes.
Setting the ECCFn bit in a PCA0CPMn register enables the module’s CCFn
interrupt. Note: PCA0 interrupts must be globally enabled before individual CCFn interrupts are recognized. PCA0
interrupts are globally enabled by setting the EA bit (IE.7) and the EPCA0 bit (EIE1.3) to logic 1. See Figure 20.2
for details on the PCA interrupt configuration.
Table 20.1. PCA0CPM Register Settings for PCA Capture/Compare Modules
ECOM
CAPP
CAPN
MAT
TOG
PWM
ECCF
Operation Mode
X
1
0
X
Capture triggered by positive edge on
CEXn
X
0
1
0
X
Capture triggered by negative edge on
CEXn
X
1
0
X
Capture triggered by transition on CEXn
1
0
1
0
X
Software Timer
1
0
1
0
X
High Speed Output
1
0
X
0
1
X
Pulse Width Modulator
X = Don’t Care
Figure 20.2. PCA Interrupt Block Diagram
PCA0CN
C
F
C
R
C
F
0
C
F
2
C
F
1
C
F
4
C
F
3
PCA0MD
C
I
D
L
E
C
F
C
P
S
1
C
P
S
0
1
PCA Module 0
PCA Module 1
ECCF1
0
1
ECCF0
0
1
PCA Module 2
ECCF2
0
1
PCA Module 3
ECCF3
0
1
PCA Module 4
ECCF4
PCA Counter/
Timer Overflow
0
1
Interrupt
Priority
Decoder
EPCA0
(EIE1.3)
0
1
EA
(IE.7)
0
1
PCA0CPMn
E
C
O
M
n
E
C
F
n
T
O
G
n
P
W
M
n
C
A
P
n
C
A
P
N
n
M
A
T
n
(for n = 0 to 4)
155
Rev. 1.7
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