參數(shù)資料
型號: C8051F010
廠商: Silicon Laboratories Inc
文件頁數(shù): 68/171頁
文件大?。?/td> 0K
描述: IC 8051 MCU 32K FLASH 64TQFP
標準包裝: 160
系列: C8051F01x
核心處理器: 8051
芯體尺寸: 8-位
速度: 20MHz
連通性: SMBus(2 線/I²C),SPI,UART/USART
外圍設(shè)備: 欠壓檢測/復(fù)位,POR,PWM,溫度傳感器,WDT
輸入/輸出數(shù): 32
程序存儲器容量: 32KB(32K x 8)
程序存儲器類型: 閃存
RAM 容量: 256 x 8
電壓 - 電源 (Vcc/Vdd): 2.7 V ~ 3.6 V
數(shù)據(jù)轉(zhuǎn)換器: A/D 8x10b; D/A 2x12b
振蕩器型: 內(nèi)部
工作溫度: -40°C ~ 85°C
封裝/外殼: 64-TQFP
包裝: 托盤
C8051F000/1/2/5/6/7
C8051F010/1/2/5/6/7
1.4.
Programmable Digital I/O and Crossbar
The standard 8051 Ports (0, 1, 2, and 3) are available on the MCUs.
All four ports are pinned out on the
F000/05/10/15.
Ports 0 and 1 are pinned out on the F001/06/11/16, and only Port 0 is pinned out on the
F002/07/12/17. The Ports not pinned out are still available for software use as general purpose registers. The Port
I/O behave like the standard 8051 with a few enhancements.
Each Port I/O pin can be configured as either a push-pull or open-drain output. Also, the “weak pull-ups” which are
normally fixed on an 8051 can be globally disabled, providing additional power saving capabilities for low power
applications.
Perhaps the most unique enhancement is the Digital Crossbar. This is essentially a large digital switching network
that allows mapping of internal digital system resources to Port I/O pins on P0, P1, and P2. (See Figure 1.8.)
Unlike microcontrollers with standard multiplexed digital I/O, all combinations of functions are supported.
The on-board counter/timers, serial buses, HW interrupts, ADC Start of Conversion input, comparator outputs, and
other digital signals in the controller can be configured to appear on the Port I/O pins specified in the Crossbar
Control registers. This allows the user to select the exact mix of general purpose Port I/O and digital resources
needed for his particular application.
Figure 1.8. Digital Crossbar Diagram
XBR0, XBR1,
XBR2 Registers
PRT3CF
Register
External
Pins
P0
P1
P2
8
(I
nt
ernal
Di
git
a
lSi
gnals)
Port
Latches
P3
I/O
Cells
P3.0
Digital
Crossbar
Priority
Decoder
P1
I/O
Cells
SMBus
2
SPI
4
UART
2
PCA
6
T0, T1,
T2
6
SYSCLK
CNVSTR
P3.7
P1.0
P1.7
P2
I/O
Cells
P2.0
P2.7
P0
I/O
Cells
P0.0
P0.7
8
Highest
Priority
Lowest
Priority
Highest
Priority
Lowest
Priority
8
(P2.0-P2.7)
(P1.0-P1.7)
(P0.0-P0.7)
8
PRT0CF, PRT1CF,
PRT2CF Registers
(P3.0-P3.7)
Comptr.
Outputs
2
Rev. 1.7
16
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