參數(shù)資料
型號: C8051F011
廠商: Silicon Laboratories Inc
文件頁數(shù): 158/171頁
文件大?。?/td> 0K
描述: IC 8051 MCU 32K FLASH 48TQFP
標準包裝: 250
系列: C8051F01x
核心處理器: 8051
芯體尺寸: 8-位
速度: 20MHz
連通性: SMBus(2 線/I²C),SPI,UART/USART
外圍設(shè)備: 欠壓檢測/復位,POR,PWM,溫度傳感器,WDT
輸入/輸出數(shù): 16
程序存儲器容量: 32KB(32K x 8)
程序存儲器類型: 閃存
RAM 容量: 256 x 8
電壓 - 電源 (Vcc/Vdd): 2.7 V ~ 3.6 V
數(shù)據(jù)轉(zhuǎn)換器: A/D 8x10b; D/A 2x12b
振蕩器型: 內(nèi)部
工作溫度: -40°C ~ 85°C
封裝/外殼: 48-TQFP
包裝: 托盤
C8051F000/1/2/5/6/7
C8051F010/1/2/5/6/7
11. FLASH MEMORY
These devices include 32k + 128 bytes of on-chip, reprogrammable Flash memory for program code and non-
volatile data storage. The Flash memory can be programmed in-system, a single byte at a time, through the JTAG
interface or by software using the MOVX instruction. Once cleared to 0, a Flash bit must be erased to set it back to
1. The bytes would typically be erased (set to 0xFF) before being reprogrammed. The write and erase operations
are automatically timed by hardware for proper execution. Data polling to determine the end of the write/erase
operation is not required. The Flash memory is designed to withstand at least 20,000 write/erase cycles. Refer to
Table 11.1 for the electrical characteristics of the Flash memory.
11.1.
Programming The Flash Memory
The simplest means of programming the Flash memory is through the JTAG interface using programming tools
provided by Silicon Labs or a third party vendor. This is the only means for programming a non-initialized device.
For details on the JTAG commands to program Flash memory, see Section 21.2.
The Flash memory can be programmed by software using the MOVX instruction with the address and data byte to
be programmed provided as normal operands.
Before writing to Flash memory using MOVX, Flash write
operations must be enabled by setting the PSWE Program Store Write Enable bit (PSCTL.0) to logic 1. Writing to
Flash remains enabled until the PSWE bit is cleared by software.
Writes to Flash memory can clear bits but cannot set them. Only an erase operation can set bits in Flash. Therefore,
the byte location to be programmed must be erased before a new value can be written. The 32kbyte Flash memory
is organized in 512-byte sectors. The erase operation applies to an entire sector (setting all bytes in the sector to
0xFF). Setting the PSEE Program Store Erase Enable bit (PSCTL.1) and PSWE (PSCTL.0) bit to logic 1 and then
using the MOVX command to write a data byte to any byte location within the sector will erase an entire 512-byte
sector. The data byte written can be of any value because it is not actually written to the Flash. Flash erasure
remains enabled until the PSEE bit is cleared by software. The following sequence illustrates the algorithm for
programming the Flash memory by software:
1.
Enable Flash Memory write/erase in FLSCL Register using FLASCL bits.
2.
Set PSEE (PSCTL.1) to enable Flash sector erase.
3.
Set PSWE (PSCTL.0) to enable Flash writes.
4.
Use MOVX to write a data byte to any location within the 512-byte sector to be erased.
5.
Clear PSEE to disable Flash sector erase.
6.
Use MOVX to write a data byte to the desired byte location within the erased 512-byte sector. Repeat until
finished. (Any number of bytes can be written from a single byte to and entire sector.)
7.
Clear the PSWE bit to disable Flash writes.
Write/Erase timing is automatically controlled by hardware based on the prescaler value held in the Flash Memory
Timing Prescaler register (FLSCL). The 4-bit prescaler value FLASCL determines the time interval for write/erase
operations. The FLASCL value required for a given system clock is shown in Figure 11.4, along with the formula
used to derive the FLASCL values. When FLASCL is set to 1111b, the write/erase operations are disabled. Note
that code execution in the 8051 is stalled while the Flash is being programmed or erased.
Table 11.1. FLASH Memory Electrical Characteristics
VDD = 2.7 to 3.6V, -40
C to +85C unless otherwise specified.
PARAMETER
CONDITIONS
MIN
TYP
MAX
UNITS
Endurance
20k
100k
Erase/Wr
Erase Cycle Time
10
ms
Write Cycle Time
40
s
87
Rev. 1.7
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