參數(shù)資料
型號: C8051F206R
廠商: Silicon Laboratories Inc
文件頁數(shù): 17/146頁
文件大?。?/td> 0K
描述: IC 8051 MCU 8K FLASH 48TQFP
標(biāo)準(zhǔn)包裝: 1
系列: C8051F2xx
核心處理器: 8051
芯體尺寸: 8-位
速度: 25MHz
連通性: SPI,UART/USART
外圍設(shè)備: 欠壓檢測/復(fù)位,POR,WDT
輸入/輸出數(shù): 32
程序存儲器容量: 8KB(8K x 8)
程序存儲器類型: 閃存
RAM 容量: 1.25K x 8
電壓 - 電源 (Vcc/Vdd): 2.7 V ~ 3.6 V
數(shù)據(jù)轉(zhuǎn)換器: A/D 32x12b
振蕩器型: 內(nèi)部
工作溫度: -40°C ~ 85°C
封裝/外殼: 48-TQFP
包裝: 剪切帶 (CT)
其它名稱: 336-1036-1
C8051F2xx
Rev. 1.6
113
Multiple masters may reside on the same bus. A Mode Fault flag (MODF, SPI0CN.5) is set to logic 1 when
the SPI is configured as a master (MSTEN = 1) and its slave select signal NSS is pulled low. When the
Mode Fault flag is set, the MSTEN and SPIEN bits of the SPI control register are cleared by hardware,
thereby placing the SPI module in an "off-line" state. In a multiple-master environment, the system control-
ler should check the state of the SLVSEL flag (SPI0CN.2) to ensure the bus is free before setting the
MSTEN bit and initiating a data transfer.
15.2. Serial Clock Timing
As shown in Figure 15.4, four combinations of serial clock phase and polarity can be selected using the
clock control bits in the SPI Configuration Register (SPI0CFG). The CKPHA bit (SPI0CFG.7) selects one
of two clock phases (edge used to latch the data). The CKPOL bit (SPI0CFG.6) selects between an active-
high or active-low clock. Both master and slave devices must be configured to use the same clock phase
and polarity. Note: the SPI should be disabled (by clearing the SPIEN bit, SPI0CN.0) while changing the
clock phase and polarity.
The SPI Clock Rate Register (SPI0CKR) as shown in SFR Definition 15.3 controls the master mode serial
clock frequency. This register is ignored when operating in slave mode.
Figure 15.4. Full Duplex Operation
15.3. SPI Special Function Registers
The SPI is accessed and controlled through four special function registers in the system controller:
SPI0CN Control Register, SPI0DAT Data Register, SPI0CFG Configuration Register, and SPI0CKR Clock
Rate Register. The four special function registers related to the operation of the SPI Bus are described in
the following section.
SCK
(CK POL = 0,CK PHA = 0)
SCK
(CK POL =1, CK PHA =0)
SCK
(CK POL =1, CK PHA =1)
SCK
(CK POL = 0,CK PHA =1)
MSB
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
LSB
MISO/MOSI
NSS
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