參數(shù)資料
型號(hào): C8051F206R
廠商: Silicon Laboratories Inc
文件頁數(shù): 42/146頁
文件大?。?/td> 0K
描述: IC 8051 MCU 8K FLASH 48TQFP
標(biāo)準(zhǔn)包裝: 1
系列: C8051F2xx
核心處理器: 8051
芯體尺寸: 8-位
速度: 25MHz
連通性: SPI,UART/USART
外圍設(shè)備: 欠壓檢測/復(fù)位,POR,WDT
輸入/輸出數(shù): 32
程序存儲(chǔ)器容量: 8KB(8K x 8)
程序存儲(chǔ)器類型: 閃存
RAM 容量: 1.25K x 8
電壓 - 電源 (Vcc/Vdd): 2.7 V ~ 3.6 V
數(shù)據(jù)轉(zhuǎn)換器: A/D 32x12b
振蕩器型: 內(nèi)部
工作溫度: -40°C ~ 85°C
封裝/外殼: 48-TQFP
包裝: 剪切帶 (CT)
其它名稱: 336-1036-1
C8051F2xx
136
Rev. 1.6
17.2.3. Mode 2: Baud Rate Generator
Timer 2 can be used as a baud rate generator for the serial port (UART) when the UART is operated in
modes 1 or 3 (refer to Section 16.1 for more information on UART operational modes). In Baud Rate Gen-
erator mode, Timer 2 works similarly to the auto-reload mode. On overflow, the 16-bit value held in the two
capture registers (RCAP2H, RCAP2L) is automatically loaded into the counter/timer register. However, the
TF2 overflow flag is not set and no interrupt is generated. Instead, the overflow event is used as the input
to the UART's shift clock. Timer 2 overflows can be used to generate baud rates for transmit and/or
receive independently.
The Baud Rate Generator mode is selected by setting RCLK (T2CON.5) and/or TCLK (T2CON.4) to logic
one. When RCLK or TCLK is set to logic 1, Timer 2 operates in the auto-reload mode regardless of the
state of the CP/RL2 bit. The baud rate for the UART, when operating in mode 1 or 3, is determined by the
Timer 2 overflow rate:
Baud Rate = Timer 2 Overflow Rate / 16.
Note, in all other modes, the time base for the timer is the system clock divided by one or twelve as
selected by the T2M bit in CKCON. However, in Baud Rate Generator mode, the time base is the system
clock divided by two. No other divisor selection is possible. If a different time base is required, setting the
C/T2 bit to logic 1 will allow the time base to be derived from the external input pin T2. In this case, the
baud rate for the UART is calculated as:
Baud Rate = FCLK / [32 x (65536 – [RCAP2H:RCAP2L]) ]
Where FCLK is the frequency of the signal supplied to T2 and [RCAP2H:RCAP2L] is the 16-bit value held
in the capture registers.
As explained above, in Baud Rate Generator mode, Timer 2 does not set the TF2 overflow flag and there-
fore cannot generate an interrupt. However, if EXEN2 is set to logic 1, a high-to-low transition on the T2EX
input pin will set the EXF2 flag and a Timer 2 interrupt will occur if enabled. Therefore, the T2EX input may
be used as an additional external interrupt source.
Figure 17.6. T2 Mode 2 Block Diagram
TL2
TH2
EXEN2
T2EX
TR2
T2
SYSCLK
C/T2
2
1
0
Interrupt
TCLK
RCAP2L
RCAP2H
Reload
2
16
Timer 1
Overflow
RX Clock
TX Clock
TCLK
RCLK
T2
C
O
N
RCLK
TCLK
EXF2
EXEN2
TR2
C/T2
CP/RL2
TF2
PORT0
MUX
PORT0
MUX
PCON
S
M
O
D
G
F
1
G
F
0
S
T
O
P
I
D
L
E
1
0
1
0
1
0
Timer 2
Overflow
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