參數(shù)資料
型號: C8051F221R
廠商: Silicon Laboratories Inc
文件頁數(shù): 88/146頁
文件大?。?/td> 0K
描述: IC 8051 MCU 8K FLASH 32LQFP
標準包裝: 1
系列: C8051F2xx
核心處理器: 8051
芯體尺寸: 8-位
速度: 25MHz
連通性: SPI,UART/USART
外圍設備: 欠壓檢測/復位,POR,WDT
輸入/輸出數(shù): 22
程序存儲器容量: 8KB(8K x 8)
程序存儲器類型: 閃存
RAM 容量: 256 x 8
電壓 - 電源 (Vcc/Vdd): 2.7 V ~ 3.6 V
數(shù)據(jù)轉(zhuǎn)換器: A/D 22x8b
振蕩器型: 內(nèi)部
工作溫度: -40°C ~ 85°C
封裝/外殼: 32-LQFP
包裝: 剪切帶 (CT)
其它名稱: 336-1009-1
C8051F2xx
46
Rev. 1.6
6.3.
ADC Programmable Window Detector
The ADC programmable window detector is very useful in many applications. It continuously compares
the ADC output to user-programmed limits and notifies the system when an out-of-band condition is
detected. This is especially effective in an interrupt-driven system, saving code space and CPU bandwidth
while delivering faster system response times. The window detector interrupt flag (ADWINT in ADC0CN)
can also be used in polled mode. The high and low bytes of the reference words are loaded into the ADC
Greater-Than and ADC Less-Than registers (ADC0GTH, ADC0GTL, ADC0LTH, and ADC0LTL).
Figure 6.3 and Figure 6.4 show example comparisons for reference. Notice that the window detector flag
can be asserted when the measured data is inside or outside the user-programmed limits, depending on
the programming of the ADC0GTx and ADC0LTx registers.
SFR Definition 6.6. ADC0GTH: ADC Greater-Than Data High Byte (C8051F206)
SFR Definition 6.7. ADC0GTL: ADC Greater-Than Data Low Byte (C8051F206)
SFR Definition 6.8. ADC0LTH: ADC Less-Than Data High Byte (C8051F206)
Bits7–0:
The high byte of the ADC Greater-Than Data Word.
R/W
Reset Value
11111111
Bit7
Bit6
Bit5
Bit4
Bit3
Bit2
Bit1
Bit0
SFR Address:
0xC5
Bits7–0:
The low byte of the ADC Greater-Than Data Word.
Definition: ADC Greater-Than Data Word = ADC0GTH:ADC0GTL
R/WR/WR/WR/WR/WR/W
R/WR/W
Reset Value
11111111
Bit7
Bit6
Bit5
Bit4
Bit3
Bit2
Bit1
Bit0
SFR Address:
0xC4
Bits7–0:
The high byte of the ADC Less-Than Data Word.
R/W
Reset Value
11111111
Bit7
Bit6
Bit5
Bit4
Bit3
Bit2
Bit1
Bit0
SFR Address:
0xC4
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