參數(shù)資料
型號: C8051F305-GS
廠商: Silicon Laboratories Inc
文件頁數(shù): 92/178頁
文件大?。?/td> 0K
描述: IC 8051 MCU 2K FLASH 14-SOIC
產(chǎn)品培訓模塊: Serial Communication Overview
標準包裝: 56
系列: C8051F30x
核心處理器: 8051
芯體尺寸: 8-位
速度: 25MHz
連通性: SMBus(2 線/I²C),UART/USART
外圍設備: POR,PWM,WDT
輸入/輸出數(shù): 8
程序存儲器容量: 2KB(2K x 8)
程序存儲器類型: 閃存
RAM 容量: 256 x 8
電壓 - 電源 (Vcc/Vdd): 2.7 V ~ 3.6 V
振蕩器型: 外部
工作溫度: -40°C ~ 85°C
封裝/外殼: 14-SOIC(0.154",3.90mm 寬)
包裝: 管件
產(chǎn)品目錄頁面: 622 (CN2011-ZH PDF)
配用: 336-1444-ND - ADAPTER PROGRAM TOOLSTICK F300
其它名稱: 336-1540-5
C8051F300/1/2/3/4/5
20
Rev. 2.9
Perhaps the most unique Port I/O enhancement is the Digital Crossbar. This is essentially a digital switch-
ing network that allows mapping of internal digital system resources to Port I/O pins (See Figure 1.7). On-
chip counter/timers, serial buses, HW interrupts, comparator output, and other digital signals in the control-
ler can be configured to appear on the Port I/O pins specified in the Crossbar Control registers. This allows
the user to select the exact mix of general purpose Port I/O and digital resources needed for the particular
application.
Figure 1.7. Digital Crossbar Diagram
1.5.
Serial Ports
The C8051F300/1/2/3/4/5 Family includes an SMBus/I2C interface and a full-duplex UART with enhanced
baud rate configuration. Each of the serial buses is fully implemented in hardware and makes extensive
use of the CIP-51's interrupts, thus requiring very little CPU intervention.
XBR0, XBR1,
XBR2 Registers
Digital
Crossbar
Priority
Decoder
SYSCLK
2
(In
te
rnal
D
igital
Sign
als)
Highest
Priority
Lowest
Priority
P0
I/O
Cells
P0.0
P0.7
8
P0MDOUT,
P0MDIN Registers
SMBus
UART
T0, T1
2
4
PCA
P0
Port Latch
(P0.0-P0.7)
8
CP0
Outputs
2
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