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參數(shù)資料
| 型號： | C8051T600QDB |
| 廠商： | Silicon Laboratories Inc |
| 文件頁數(shù)： | 183/188頁 |
| 文件大小： | 0K |
| 描述： | BOARD SOCKET DAUGHTER QFN |
| 標(biāo)準(zhǔn)包裝： | 1 |
| 模塊/板類型： | QFN 插口模塊 |
| 適用于相關(guān)產(chǎn)品： | C8051T600DK |
| 其它名稱： | 336-1406 |
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C8051T600/1/2/3/4/5/6
94
Rev. 1.2
19.2. Power-Fail Reset/VDD Monitor
When a power-down transition or power irregularity causes VDD to drop below VRST, the power supply
monitor will drive the RST pin low and hold the CIP-51 in a reset state (see Figure 19.2). When VDD returns
to a level above VRST, the CIP-51 will be released from the reset state. Note that even though internal data
memory contents are not altered by the power-fail reset, it is impossible to determine if VDD dropped below
the level required for data retention. If the PORSF flag reads 1, the data may no longer be valid. The VDD
monitor is disabled after power-on resets. Its defined state (enabled/disabled) is not altered by any other
reset source. For example, if the VDD monitor is enabled by code and a software reset is performed, the
VDD monitor will still be enabled after the reset.
Important Note: If the VDD monitor is being turned on from a disabled state, it has the potential to gener-
ate a system reset. The VDD monitor is enabled and selected as a reset source by writing the PORSF flag
in RSTSRC to 1.
See Figure 19.2 for VDD monitor timing; note that the power-on-reset delay is not incurred after a VDD
19.3. External Reset
The external RST pin provides a means for external circuitry to force the device into a reset state. Assert-
ing an active-low signal on the RST pin generates a reset; an external pullup and/or decoupling of the RST
pin may be necessary to avoid erroneous noise-induced resets. See Table 8.4 for complete RST pin spec-
ifications. The PINRSF flag (RSTSRC.0) is set on exit from an external reset.
19.4. Missing Clock Detector Reset
The Missing Clock Detector (MCD) is a one-shot circuit that is triggered by the system clock. If the system
clock remains high or low for more than the time specified in Section “8. Electrical Characteristics” on
page 30, the one-shot will time out and generate a reset. After a MCD reset, the MCDRSF flag (RST-
SRC.2) will read 1, signifying the MCD as the reset source; otherwise, this bit reads 0. Writing a 1 to the
MCDRSF bit enables the Missing Clock Detector; writing a 0 disables it. The state of the RST pin is unaf-
fected by this reset.
19.5. Comparator0 Reset
Comparator0 can be configured as a reset source by writing a 1 to the C0RSEF flag (RSTSRC.5).
Comparator0 should be enabled and allowed to settle prior to writing to C0RSEF to prevent any turn-on
chatter on the output from generating an unwanted reset. The Comparator0 reset is active-low: if the non-
inverting input voltage (on CP0+) is less than the inverting input voltage (on CP0-), the device is put into
the reset state. After a Comparator0 reset, the C0RSEF flag (RSTSRC.5) will read 1 signifying
Comparator0 as the reset source; otherwise, this bit reads 0. The state of the RST pin is unaffected by this
reset.
19.6. PCA Watchdog Timer Reset
The watchdog timer (WDT) function of the programmable counter array (PCA) can be used to prevent soft-
ware from running out of control during a system malfunction. The PCA WDT function can be enabled or
disabled by software as described in Section “26.4. Watchdog Timer Mode” on page 170; the WDT is
enabled and clocked by SYSCLK/12 following any reset. If a system malfunction prevents user software
from updating the WDT, a reset is generated and the WDTRSF bit (RSTSRC.5) is set to 1. The state of the
RST pin is unaffected by this reset.
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| C8051T600SDB | 功能描述:子卡和OEM板 SOIC Socket Daughter Board RoHS:否 制造商:BeagleBoard by CircuitCo 產(chǎn)品:BeagleBone LCD4 Boards 用于:BeagleBone - BB-Bone - Open Source Development Kit |
| C8051T600-SDB | 制造商:Silicon Laboratories Inc 功能描述:Evaluation Board For Mixed Signal OTP EPROM MCU Family 制造商:Silicon Laboratories Inc 功能描述:SOIC SOCKET DAUGHTER BOARD FOR C8051T60X - Boxed Product (Development Kits) |
| C8051T601 | 制造商:SILABS 制造商全稱:SILABS 功能描述:Mixed Signal OTP EPROM MCU Family |
| C8051T601-GM | 功能描述:8位微控制器 -MCU 8K OTP 11Pin QFN RoHS:否 制造商:Silicon Labs 核心:8051 處理器系列:C8051F39x 數(shù)據(jù)總線寬度:8 bit 最大時鐘頻率:50 MHz 程序存儲器大小:16 KB 數(shù)據(jù) RAM 大小:1 KB 片上 ADC:Yes 工作電源電壓:1.8 V to 3.6 V 工作溫度范圍:- 40 C to + 105 C 封裝 / 箱體:QFN-20 安裝風(fēng)格:SMD/SMT |
| C8051T601-GMR | 功能描述:8位微控制器 -MCU 8K OTP 11Pin QFN RoHS:否 制造商:Silicon Labs 核心:8051 處理器系列:C8051F39x 數(shù)據(jù)總線寬度:8 bit 最大時鐘頻率:50 MHz 程序存儲器大小:16 KB 數(shù)據(jù) RAM 大小:1 KB 片上 ADC:Yes 工作電源電壓:1.8 V to 3.6 V 工作溫度范圍:- 40 C to + 105 C 封裝 / 箱體:QFN-20 安裝風(fēng)格:SMD/SMT |
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