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參數(shù)資料
| 型號(hào)： | C9531CY |
| 英文描述： | Single bilateral switch |
| 中文描述： | CPU系統(tǒng)時(shí)鐘發(fā)生器| SSOP封裝| 28腳|塑料 |
| 文件頁(yè)數(shù)： | 4/14頁(yè) |
| 文件大?。?/td> | 176K |
| 代理商： | C9531CY |
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PCIX I/O System Clock Generator With EMI Control Features
Cypress Semiconductor Corporation
525 Los Coches St.
Milpitas, CA 95035. Tel: 408-263-6300, Fax: 408-263-6571
http://www.cypress.com
Document#: 38-07034 Rev. **
05/02/2001
Page 4 of 14
APPROVED PRODUCT
C9531
2-Wire SMBus Control Interface
The 2-wire control interface implements a write slave only interface according to SMBus specification. The device can
be read back. Sub addressing is not supported, thus all preceding bytes must be sent in order to change one of the
control bytes. The 2-wire control interface allows each clock output to be individually enabled or disabled. 100
Kbits/second (standard mode) data transfer is supported.
Through the use of the IA0, IA1, and IA2 pins the SMBus address of the device may be changed so that multiple
devices may reside on a single SMBus control signaling bus and not interfere with each other.
SMBus Address Selection Table
SMBus address of the device
DE
DC
DA
D8
D6
D4
D0
D2
IA0 BIT (Pin 10)
0
1
0
1
0
1
0
1
IA1 BIT (Pin 11)
0
0
1
1
0
0
1
1
IA2 BIT (Pin 12)
0
0
0
0
1
1
1
1
During normal data transfer, the SDATA signal only changes when the SCLK signal is low, and is stable when SCLK is
high. There are two exceptions to this. A high to low transition on SDATA while SCLK is high is used to indicate the
start of a data transfer cycle. A low to high transition on SDATA while SCLK is high indicates the end of a data transfer
cycle. Data is always sent as complete 8-bit bytes, after which an acknowledge is generated. The first byte of a
transfer cycle is a 7-bit address with a Read/Write bit (R/W#) as the LSB. R/W# = 1 in read mode.
The device will respond to writes to 10 bytes (max) of data to its selected address by generating the acknowledge (low)
signal on the SDATA wire following reception of each byte.
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