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參數(shù)資料
| 型號： | C9805CYB |
| 英文描述： | Quad line receivers |
| 中文描述： | CPU系統(tǒng)時(shí)鐘發(fā)生器 |
| 文件頁數(shù)： | 3/10頁 |
| 文件大小： | 102K |
| 代理商： | C9805CYB |
C9805
Low EMI Clock Generator for Pentium
II CPU Systems with Power Management
Approved Product
INTERNATIONAL MICROCIRCUITS, INC. 525 LOS COCHES ST.
MILPITAS, CA 95035 TEL: 408-263-6300 ext. 275 FAX 408-263-6571
http://www.imicorp.com
Rev 1.5
9/2/1999
Page 3 of 10
SEL
133/100#
0
0
0
0
1
1
1
1
SEL1
0
0
1
1
0
0
1
1
SEL0
0
1
0
1
0
1
0
1
CPU
High-Z
105
100 MHz*
100 MHz*
REF/2
139.7 MHz
133 MHz
133 MHz
CPU/2
High-Z
52.5
50 MHz*
50 MHz*
REF/4
69.8 MHz
66.6 MHz
66.6 Mhz
3V66
High-Z
66.6 MHz
66.6 MHz*
66.6 MHz*
REF/4
66.6 MHz
66.6 MHz
66.6 MHz
PCI
High-Z
33.3 MHz
33.3 MHz*
33.3 MHz*
REF/8
33.3 MHz
33.3 MHz
33.3 MHz
48M
High-Z
48 MHz
OFF
48 MHz
REF/2
48 MHz
OFF
48 MHz
REF
High-Z
14.5 MHz
14.3 MHz
14.3 MH
REF
14.3 MHz
14.3 MH
14.3 MHz
IOAPIC
High-Z
16.67 MHz
16.67MHz*
16.67MHz*
REF/16
16.67 MHz
16.67MHz
16.67MHz
IOAPIC Clock Synchronization
This device incorporates IOAPIC clock synchronization. With this feature, the IOAPIC clocks are derived from the CPU
clock and represent a devided by 8 (133 MHz CPU clock mode) or divided by 6 (100 MHz CPU clock mode) clock. the
IOAPIC clock lags the CPU clock by the specified 1.5 to 4.0 nSEC.
Power Management Functions
All PCI (excluding PCI_F) and CPU clocks can be enabled or stopped via the PSTOP and CSTOP input pins. All clocks
are stopped in the low state. All clocks maintain a valid high period on transitions from running to stopped and on
transitions from stopped to running when the chip was not powered down. On power up, (after bring PD from a low to
high state) the VCOs will stabilize to the correct pulse widths within about 0.2 mS. The CPU, and PCI clocks transition
between running and stopped by waiting for one positive edge on PCI_F followed by a negative edge on the clock of
interest, after which high levels of the output are either enabled or disabled.
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