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參數(shù)資料
| 型號： | C9822EQ |
| 英文描述： | Up to 5A ULDO linear regulator |
| 中文描述： | 單時鐘驅(qū)動器| SSOP封裝| 24針|塑料 |
| 文件頁數(shù)： | 10/19頁 |
| 文件大小： | 123K |
| 代理商： | C9822EQ |
Direct Rambus
III Clock Generator
Cypress Semiconductor Corporation
525 Los Coches St.
Milpitas, CA 95035. Tel: 408-263-6300, Fax: 408-263-6571
http://www.cypress.com
Document#: 38-07093 Rev. **
05/04/2001
Page 10 of 19
APPROVED PRODUCT
C9822
Mult Transition Timing Diagrams
Clk/ClkB
Mult0 and/
or Mult1
t
MULT
Figure: 8
Transition Specifications
Transition
From
To
Transition Latency
(target spec)
Symbol
tPOWERUP
Description
Max
3 ms
A
Powerdown
Normal
Time from PwrDnB to Clk/ClkB output settled
(excluding tDISTLOCK).
Time from PwrDnB to when the internal PLL
and clock has turned on and settled.
Time from Vdd is applied and settled to Clk/ClkB
output settled (excluding tDISTLOCK).
Time from Vdd is applied and settled to the
internal PLL and clock has turned on and settled.
Time from Mult0 or Mult1 change to Clk/ClkB
output re-settled (excluding tDISTLOCK).
Time from StopB to when Clk/ClkB provides
glitch-free clock edges.
Time from stopB to Clk/ClkB output settled to
within 50 ps of the phase before StopB was
disabled.
Time from StopB to Clk/BlkB output disabled.
Time from PwerDnB to the device in
Powerdown.
C
Powerdown
Clk Stop
tPOWERUP
3 ms
G
Vdd on
Normal
tPOWERUP
3 ms
H
Vdd on
Clk Stop
tPOWERUP
3 ms
J
Normal
Normal
tMULT
1 ms
E
Clk Stop
Normal
tCLKON
10 ns
E
Clk Stop
Normal
tCLKSETL
20
cycles
F
Normal
Normal or
Clk Stop
Clk Stop
Powerdown
tCLKOFF
tPOWERDN
5 ns
1ms
B,D
Table 7: State Transition Latency Specifications
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