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參數(shù)資料
| 型號(hào)： | C9822EQ |
| 英文描述： | Up to 5A ULDO linear regulator |
| 中文描述： | 單時(shí)鐘驅(qū)動(dòng)器| SSOP封裝| 24針|塑料 |
| 文件頁數(shù)： | 2/19頁 |
| 文件大小： | 123K |
| 代理商： | C9822EQ |
Direct Rambus
III Clock Generator
Cypress Semiconductor Corporation
525 Los Coches St.
Milpitas, CA 95035. Tel: 408-263-6300, Fax: 408-263-6571
http://www.cypress.com
Document#: 38-07093 Rev. **
05/04/2001
Page 2 of 19
APPROVED PRODUCT
C9822
Pin Description
Pin No.
2
6
Pin Name
REFCLK
PCLKM
I/O
I
I
Description
Reference clock input. Normally supplied by a system clock source generator.
Phase detector input: The phase difference between this signal and SYNCLKN is
used to synchronize the Rambus
channel Clock with the system clock. Both the
PCLKM and SYNCLKN are provided by the memory controller. If the gear ratio is
not used, connect this pin to ground.
Phase detector input: The phase difference between this signal and PCLKM is
used to synchronize the Rambus
Channel Clock with the system clock. PCLKM
and SYNCLKN are provided by the memory controller. If the gear ratio is not
used, connect this pin to ground.
Clock Stop. When this input is driven to low state, the differential Rambus
channel clocks are disabled.
Power Down. When this input is driven to a logic low level, the differential
Rambus
channel clocks are disabled and the system clock generator is placed
in a power-down mode.
PLL Multiplier Select: These inputs select the PLL prescaler and feedback
dividers to determine the multiply ratio for the PLL from the input REFLCK.
Differential Rambus
channel clock outputs.
These input pins control the operating mode of the device.
7
SYNCLKN
I
11
STOPB
I
12
PWRDNB
I
15, 14
MULT (0:1)
I
18, 20
24, 23
13
19
1
10
9
CLKB, CLK
S0, S1, S2
O
I
NC
-
No Connect. DO NOT CONNECT ANY VOLTAGE LEVELS TO THIS PIN.
Base voltage reference level for the device’s input reference clock.
Base voltage reference for the PCLKM, SYNCLKN, and STOPB.
Power supply connection for the devices phase aligner circuitry. Connected to
3.3V supply.
Power supply for Analog PLL circuitry. Connected to 3.3V supply.
Power supply clock output buffers. Connected to 3.3V supply. Care should be
taken when routing these power supply connections so as to not have their power
supply current is adequately bypassed (as close to the device as possible) and
their switching noise (surges) does not couple into the other device power
supplies.
Power supply ground return connection for the devices phase aligner circuitry.
Connected to system ground.
Reference supply ground for control input signals.
Power supply ground return connection for Analog PLL circuitry. Should be
connected to system ground potential through a well bypassed path.
System Ground for clock output buffers. Care should be taken when routing these
power return connections so as to not have their power return current shared with
other power return paths of the device.
A bypass capacitor (0.1
μ
F) should be placed as close as possible to each Vdd pin. If these bypass
capacitors are not close to the pins their high frequency filtering characteristic will be canceled by the lead
inductance’s of the traces.
VDDIR
VDDIPD
VDDC
RefV
RefV
P
3
VDDP
VDDO
P
P
16, 22
8
VSSC
P
5
4
VSSI
VSSP
P
P
17, 21
VSSO
P
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