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2-111
CA3130, CA3130A
FIGURE 1. SCHEMATIC DIAGRAM OF THE CA3130 SERIES
3
2
1
8
4
6
7
Q1
Q2
Q4
D1
D2
D3
D4
Q3
Q5
D5
D6
D7
D8
Q9
Q10
Q6
Q7
5
Z1
8.3V
INPUT STAGE
R3
1k
R4
1k
R6
1k
R5
1k
NON-INV.
INPUT
INV.-INPUT
+
-
R1
40k
5k
R2
BIAS CIRCUIT
CURRENT SOURCE FOR
Q6 AND Q7
“CURRENT SOURCE
LOAD” FOR Q11
V+
OUTPUT
OUTPUT
STAGE
Q8
Q12
V-
Q11
SECOND
STAGE
OFFSET NULL
COMPENSATION
STROBING
NOTE: DIODES D5 THROUGH D8 PROVIDE GATE-OXIDE
PROTECTION FOR MOSFET INPUT STAGE
Circuit Description
Figure 2 is a block diagram of the CA3130 Series CMOS
Operational Amplifiers. The input terminals may be operated
down to 0.5 V below the negative supply rail, and the output
can be swung very close to either supply rail in many appli-
cations. Consequently, the CA3130 Series circuits are ideal
for single-supply operation. Three Class A amplifier stages,
having the individual gain capability and current consump-
tion shown in Figure 2, provide the total gain of the CA3130.
A biasing circuit provides two potentials for common use in
the first and second stages. Term. 8 can be used both for
phase compensation and to strobe the output stage into qui-
escence. When Term. 8 is tied to the negative supply rail
(Term. 4) by mechanical or electrical means, the output
potential at Term. 6 essentially rises to the positive supply-
rail potential at Term. 7. This condition of essentially zero
current drain in the output stage under the strobed “OFF”
condition can only be achieved when the ohmic load resis-
tance presented to the amplifier is very high (e.g.,when the
amplifier output is used to drive CMOS digital circuits in
Comparator applications).
Input Stages
The circuit of the CA3130 is shown in Figure 1. It consists of
a differential-input stage using PMOS field-effect transistors
(Q6, Q7) working into a mirror-pair of bipolar transistors (Q9,
Q10) functioning as load resistors together with resistors R3
through R6. The mirror-pair transistors also function as a dif-
ferential-to-single-ended converter to provide base drive to
the second-stage bipolar transistor (Q11). Offset nulling,
when desired, can be effected by connecting a 100,000
potentiometer across Terms. 1 and 5 and the potentiometer
slider arm to Term. 4. Cascade-connected PMOS transistors
Q2, Q4 are the constant-current source for the input stage.
The biasing circuit for the constant-current source is subse-
quently described. The small diodes D5 through D8 provide
gate-oxide protection against high-voltage transients, includ-
ing static electricity during handling for Q6 and Q7.
Second-Stage
Most of the voltage gain in the CA3130 is provided by the
second amplifier stage, consisting of bipolar transistor Q11
and its cascade-connected load resistance provided by