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參數(shù)資料
| 型號： | CA95C09-16CT |
| 元件分類： | 加密電路 |
| 英文描述： | TELECOM, DATA ENCRYPTION CIRCUIT, PQFP44 |
| 封裝： | TQFP-44 |
| 文件頁數(shù)： | 29/42頁 |
| 文件大小： | 180K |
| 代理商： | CA95C09-16CT |
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Tundra Semiconductor Corporation
CA95C68/18/09
Tundra Semiconductor Corporation
3-59
Maximum Throughput
The pipelined architecture of the DES DCPs allows
simultaneous input, ciphering, and output operations.
Maximum throughput is obtained when the device is
congured for one of the dual port congurations. Figure 3-
22 shows the timing for ciphering one block of 64 bits in
either ECB or CBC modes of encryption. The inputting of
the 64 bits of data takes 8 clock cycles to complete with one
data strobe being issued per clock cycle. This data must then
be transferred from the Input Register to the algorithm
processing unit and the ags updated, which requires 5
additional clock cycles. The algorithm unit begins ciphering
concurrently with the transfer and once the ags have been
updated another 64 bit block may be entered. The ciphering
of the rst block is completed after 18 clock cycles have
elapsed from the last byte having been written to the Input
Register. Another 5 clock cycles are required to transfer the
ciphered data to the Output Register and update ags.
Transferring of data from the algorithm processing unit to
the Output Register can be performed concurrently with
loading new data into the DES algorithm unit. Removing the
data from the Output Register involves 8 clock cycles with
one data strobe per clock cycle. The whole procedure of
ciphering one block takes 39 cycles but because the different
operations can be overlapped, the DCP can process one
block every 18 clock cycles once fully loaded.
0
8
13
26
31
39
Clock
39 Finished reading 64-bit Block out of Output Port
31 Output Port FLAG becomes active
26 Algorithm Unit finishes processing block
13 Input Port FLAG becomes active for next Input Block
8 Algorithm Unit starts processing block
0 Start writing 64-bit Block into Input Port
Input 8
Bytes
In
Flags
Encryption/Decryption in
progress in the algorithm
unit
Out
Flags
Output
8 Bytes
Time in clock periods
Note: CA95C68 minimum clock period = 40 nanoseconds
Figure 3-22 : Detailed Timing of One Block
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