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參數(shù)資料
| 型號： | CA95C09-16CT |
| 元件分類： | 加密電路 |
| 英文描述： | TELECOM, DATA ENCRYPTION CIRCUIT, PQFP44 |
| 封裝： | TQFP-44 |
| 文件頁數(shù)： | 37/42頁 |
| 文件大?。?/td> | 180K |
| 代理商： | CA95C09-16CT |
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CA95C68/18/09
Tundra Semiconductor Corporation
3-66
Tundra Semiconductor Corporation
7)
Flag Output Assertion Timing Variant: The
AM9568/18 devices set and clear the ag output lines
immediately after the corresponding event has occurred.
The CA95C68/18/09 devices synchronize all internal
events with respect to the falling edge of the clock input.
Therefore, the ag output lines are set or cleared on the
next falling clock edge after the corresponding event has
occurred.
8)
IVE in Pipelined CBC Mode of Encryption: The
AM9568/18 presents the previous IVE instead of the
current IVE during a read IVE operation after a series of
CBC encryptions in which more than one round of data
was in the encryption pipeline. In the CA95C68/18/09
devices, the correct IVE is presented for the pipelined
CBC mode encryption scheme.
9)
Direct Control Mode, Mode Register
Encrypt/Decrypt Bit Variant: In Direct Control Mode
(DCM), the AM9568/18 adjusts the sense of the Mode
Register’s Encrypt/Decrypt bit (M4) inconsistently;
based on whether encryption or decryption is performed.
The CA95C68/18/09 always sets the Encrypt/Decrypt
bit to be the same sense as the AUX6-E/D input line in
this case.
10) Key Parity in Direct Control Mode: The AM9568/18
erroneously indicates a parity error during the loading of
keys of correct parity in Direct Control Mode. The
CA95C68/18/09 devices do not indicate a parity error in
this scenario.
11) Encrypted Key Load Parity Variant: The AM9568/18
will clear a parity error regardless of whether the last
byte of an encrypted key load has a parity error. The
CA95C68/18/09 devices will indicate the parity of the
last byte of an encrypted key load correctly, and if
required, the parity error must be cleared by one of the
specied methods.
12) Mode Register’s Encrypt/Decrypt Bit Status on a
Command Abort Reset: The AM9568/18 will not set
the Encrypt/Decrypt bit high if that bit is low and a
command is aborted. The CA95C68/18/09 devices will
reset this bit high when the Mode Register is reset
during a command abort sequence.
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