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| 型號(hào)： | CAME-PXB4360 |
| 英文描述： | 10A SCRS |
| 中文描述： | 內(nèi)容可尋址存儲(chǔ)器單元 |
| 文件頁(yè)數(shù)： | 34/66頁(yè) |
| 文件大?。?/td> | 869K |
| 代理商： | CAME-PXB4360 |
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Data Sheet
5-34
07.2000
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Status information generated by the control logic in the CAME indicates the success of
commands or detected failures. At the end of each command cycle, status information about the
current operation is transferred from the CAME to the ALP. The 4-bit status field consists of two
bits (S3,S2) with command independent information and two bits (S1,S0) with command related
details.
The data bus parity error is returned if a parity error at the data bus interface was detected by
the CAME since the last completed request. In all requests, the master CAME checks whether
the slave also accepted a request. This information is transferred at the Cascade Interface. If the
slave signals at CO(1..0) that it has recognized no request the
“cascade error” status is
generated in the master (Note: if LCI 2000..3FFF
H
is accessed in a single CAME configuration,
“cascade error” is also indicated because this case cannot be distinguished from a two-chip
configuration with a defect on the second chip). A “command cycle error” is internally set after
reading the status at the end of a request, or if a write access was performed while a command
cycle was running.
If a parity error is detected in one of the write accesses at the start of a command, the command
is discarded, internal status information is set to “parity error”, and the control logic waits for one
of the two possible final bus read accesses (address #6 or #7). After the final bus read access,
the CAME is ready for the next command cycle. After a command cycle is finished, the internal
status contains a “command cycle error”. This status is changed with the start of a new
command cycle. If the start of a command cycle is not recognized by the CAME, the error status
above is still present at the next status read access.
For S3/S2 = 1/0, coding of S1/S0 depends on the command just finished in the following way:
Status information can be read any time at address 6 and address 7.
ILJXUH
shows the conditions under which the status information changes. The five states, named as
OK, Busy, Alarm, Error(cmd), Error(parity) and shown in this figure, are coded by the status bits
S3..0. The start of a request can take place in the “OK”, “Alarm”, or “Error (cascade or command
cycle)” state. If a parity error is detected, the “Parity Error” state is entered. This state is left only
on reading of the status information. All write accesses are ignored while the status is in “Parity
Error” state. If no parity error has occurred, the command is processed. This is indicated by the
“Busy” state. In this state, writing generates a “command cycle error” and no internal register is
changed by the write access. Reading is allowed in “Busy” state. Depending on the result of the
request, either the “OK”, “Alarm”, or “Error (cascade or command cycle)” status is entered. After
reading the status once, the “Error (command cycle)” is entered. This supports the recognition
of a missing command cycle start.
at page 35
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