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| 型號： | CAN |
| 英文描述： | 8A SCRS |
| 中文描述： | [可以]恐慌影響了PLL基于CAN communicationApplication注意58K/NOV.19.03 |
| 文件頁數(shù)： | 2/6頁 |
| 文件大小： | 58K |
| 代理商： | CAN |
M32C/80 series
Effects of PLL jitters on CAN communication
REJ05B0026-0100Z/Rev.1.00
November 2003
Page 2 of 6
1. Phase timing of the PLL frequency synthesizer
The PLL in the M32C/80 series has its phases corrected every reference clock cycle. Therefore, in no case will PLL jitters
accumulate along with the passage of time.
Figure 1 shows a block diagram of the PLL. Figure 2 shows an example timing with which the PLL in the M32C/80 series is
corrected for phases. In the example in Figure 2, the reference clock is derived from XIN by dividing it by 2, and the programmable
counter is set to divide-by-16, so that XIN is multiplied by 4.
Figure 1 PLL block diagram
Figure 2 Phase correction timing
Reference
Frequency
Counter
Programable
Counter
Phase
Compare
Charge
Pomp
Voltage
Control
Oscillator
(VCO)
PLL Clock
1/2
PLC12
1/3
X
IN
(8MHz)
Phase correction timing
Reference clock
frequency (4 MHz)
PLL clock
frequency (64MHz)
CAN clock
frequency(32MHz)
Reference clock frequency : XIN frequency / Reference frequency counter value
PLL clock frequency : Reference clock frequency X Programmable counter value
CAN clock frequency : PLL clock frequency / 2
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