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| 型號： | CAN |
| 英文描述： | 8A SCRS |
| 中文描述： | [可以]恐慌影響了PLL基于CAN communicationApplication注意58K/NOV.19.03 |
| 文件頁數(shù)： | 3/6頁 |
| 文件大?。?/td> | 58K |
| 代理商： | CAN |
M32C/80 series
Effects of PLL jitters on CAN communication
REJ05B0026-0100Z/Rev.1.00
November 2003
Page 3 of 6
2. Effects of PLL jitters on CAN communication
A worst-case situation where CAN communication is most affected by an out-of-sync condition (i.e., the longest possible period for
which communication will not be resynchronized) occurs when 5 consecutive dominant bits are followed by 5 consecutive recessive
bits. If the falling edge of XIN occurs within the resynchronization width (Resynchronization Jump Width, hereafter referred to as
SJW), CAN communication will not be affected.
Figure 3 shows how CAN communication is resynchronized when 5 consecutive dominant bits are followed by 5 consecutive
recessive bits and the timing with which the PLL is corrected for phases.
Because the PLL in the M32C/80 series has its phases corrected every reference clock cycle, PLL jitters do not accumulate along
with the passage of time.
Figure 3 Relation of resynchronization on CAN communication and PLL phase correction
CAN 1bit
Resynchronous timing
1
2
3
4
5
1
2
3
4
5
X
IN
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
1
2
3
4
Reference clock
frequency
B
tw(10bit)
Because phases are corrected every reference clock, oscillation errors do not accumulate along with the passage of time.
A
tw(10bit): Time of worst-case (period of 10bits)
A:Trigger point to measure the long-term jitter of the PLL
B:The long-term jitter of the PLL occurring in tw(10bit)
Timing of the phase correction of the PLL
1bit
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