參數(shù)資料
型號(hào): CAT1161PI-42TE13
英文描述: Supervisory Circuits with I2C Serial CMOS EEPROM, Precision Reset Controller and Watchdog Timer
中文描述: 監(jiān)控電路,帶有I2C串行CMOS EEPROM的,精密復(fù)位控制器和看門狗定時(shí)器
文件頁數(shù): 3/12頁
文件大小: 69K
代理商: CAT1161PI-42TE13
3
CAT1161/2
Doc No. 3002, Rev. D
CAPACITANCE
T
A
= 25C, f = 1.0 MHz, V
CC
= 5V
Symbol
Test
C
I/O(1)
Input/Output Capacitance (SDA)
Conditions
Max
Units
V
I/O
= 0V
8
pF
C
IN(1)
Input Capacitance (SCL)
V
IN
= 0V
6
pF
V
CC
= 2.7V - 6V
Min
V
CC
= 4.5V - 5.5V
Min
SYMBOL
PARAMETER
Max
Max
Units
F
SCL
T
I(1)
Clock Frequency
Noise Suppresion Time
Constant at SCL, SDA Inputs
SLC Low to SDA Data Out
and ACK Out
Time the Bus Must be Free Before
a New Transmission Can Start
100
200
400
200
kHz
ns
t
AA
3.5
1
μ
s
t
BUF(1)
4.7
1.2
μ
s
t
HD:STA
Start Condition Hold Time
4
0.6
μ
s
μ
s
μ
s
μ
s
t
LOW
Clock Low Period
4.7
1.2
t
HIGH
t
SU:STA
Clock High Period
Start Condition Setup Time
(for a Repeated Start Condition)
4
0.6
0.6
4.7
t
HD:DAT
Data in Hold Time
0
0
ns
t
SU:DAT
Data in Setup Time
50
50
ns
t
R(1)
SDA and SCL Rise Time
1
0.3
μ
s
t
F(1)
SDA and SCL Fall Time
300
300
ns
t
SU:STO
Stop Condition Setup Time
4
0.6
μ
s
t
DH
Data Out Hold Time
100
100
ns
A.C. CHARACTERISTICS
V
CC
=2.7V to 6.0V unless otherwise specified.
Output Load is 1 TTL Gate and 100pF.
POWER-UP TIMING
(1)(2)
Symbol
Parameter
Max
Units
t
PUR
Power-up to Read Operation
1
ms
t
PUW
Power-up to Write Operation
1
ms
NOTE:
(1) This parameter is tested initially and after a design or process change that affects the parameter.
(2) t
PUR
and t
PUW
are the delays required from the time V
CC
is stable until the specific operation can be initiated.
WRITE CYCLE LIMITS
Symbol
Parameter
Min
Typ
Max
Units
t
WR
Write Cycle Time
10
ms
The write cycle time is the time from a valid stop condition of a write sequence to the end of the internal program/erase cycle. During the
write cycle, the bus interface circuits are disabled, SDA is allowed to remain high, and the device does not respond to its slave address.
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